From cd2e2021a0ac74934cd29e3856ab417da4e6058d Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 10 Nov 2022 17:54:43 +0100 Subject: [PATCH] radv: emit PA_SU_PRIM_FILTER_CNTL in the graphics preamble This register doesn't change. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_pipeline.c | 10 ---------- src/amd/vulkan/si_cmd_buffer.c | 9 +++++++++ 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index db1f95ff760..603afd384cf 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -4379,19 +4379,9 @@ static void radv_pipeline_emit_multisample_state(struct radeon_cmdbuf *ctx_cs, const struct radv_graphics_pipeline *pipeline) { - const struct radv_physical_device *pdevice = pipeline->base.device->physical_device; const struct radv_multisample_state *ms = &pipeline->ms; radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1); - - /* The exclusion bits can be set to improve rasterization efficiency - * if no sample lies on the pixel boundary (-8 sample offset). It's - * currently always TRUE because the driver doesn't support 16 samples. - */ - bool exclusion = pdevice->rad_info.gfx_level >= GFX7; - radeon_set_context_reg( - ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, - S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) | S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion)); } static void diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 2589c83df3b..f1e79249e6a 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -630,6 +630,15 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) radeon_set_uconfig_reg(cs, R_031114_SPI_GS_THROTTLE_CNTL2, 0x1544D); } + /* The exclusion bits can be set to improve rasterization efficiency if no sample lies on the + * pixel boundary (-8 sample offset). It's currently always TRUE because the driver doesn't + * support 16 samples. + */ + bool exclusion = physical_device->rad_info.gfx_level >= GFX7; + radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, + S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) | + S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion)); + si_emit_compute(device, cs); }