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radv: Include flushes in the barrier.

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Since the flushes really happen on the next draw delay the barrier
end to include the flushes.

This fixes the barrier duration in RGP.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6550>
This commit is contained in:
Bas Nieuwenhuizen
2020-09-01 17:09:19 +02:00
committed by Marge Bot
parent eff6710aab
commit cc73182152
4 changed files with 41 additions and 24 deletions
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6
src/amd/vulkan/si_cmd_buffer.c
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@@ -1424,8 +1424,10 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
RADV_CMD_FLAG_START_PIPELINE_STATS |
RADV_CMD_FLAG_STOP_PIPELINE_STATS);
if (!cmd_buffer->state.flush_bits)
if (!cmd_buffer->state.flush_bits) {
radv_describe_barrier_end_delayed(cmd_buffer);
return;
}
radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
@@ -1452,6 +1454,8 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
* should be finished at this point.
*/
cmd_buffer->pending_reset_query = false;
radv_describe_barrier_end_delayed(cmd_buffer);
}
/* sets the CP predication state using a boolean stored at va */