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anv: Fix coverage masks for VK_EXT_conservative_rasterization

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Earlier, I just tried to copy what iris was doing and, as it turns out,
copied it wrong.  Also, Vulkan doesn't have a concept of getting the
conservative coverage in the shader.  The spec for SampleMask says:

    "Decorating a variable with the SampleMask built-in decoration will
    make any variable contain the coverage mask for the current fragment
    shader invocation."

And the spec for conservative rasterization says

    "When overestimate conservative rasterization is enabled, rather
    than evaluating coverage at individual sample locations, a
    determination is made of whether any portion of the pixel (including
    its edges and corners) is covered by the primitive. If any portion
    of the pixel is covered, then all bits of the coverage mask for the
    fragment corresponding to that pixel are enabled."

Putting these two together and you get what the Intel HW docs say for
ICMS_NORMAL:

    "Input Coverage masks based on inner conservatism and factors in
    SAMPLE_MASKs. If Pixel is conservatively fully covered all samples
    are enabled."

So I'm pretty sure based on this that the right thing to do here is to
ignore conservative rasterization and leave it set to ICMS_NORMAL
whenever we're not in the post-depth-coverage special case.

While we're here, fix the silly indentation.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4565
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: d5b56debde "anv: Implement VK_EXT_conservative_rasterization"
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10017>
This commit is contained in:
Jason Ekstrand
2021-04-02 21:40:19 -05:00
committed by Marge Bot
parent 1b3a0f8829
commit cc2a4ff880
1 changed files with 5 additions and 8 deletions
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13
src/intel/vulkan/genX_pipeline.c
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@@ -2139,17 +2139,14 @@ emit_3dstate_ps_extra(struct anv_graphics_pipeline *pipeline,
ps.PixelShaderComputesStencil = wm_prog_data->computed_stencil;
ps.PixelShaderPullsBary = wm_prog_data->pulls_bary;
ps.InputCoverageMaskState = ICMS_NONE;
ps.InputCoverageMaskState = ICMS_NONE;
assert(!wm_prog_data->inner_coverage); /* Not available in SPIR-V */
if (!wm_prog_data->uses_sample_mask)
ps.InputCoverageMaskState = ICMS_NONE;
ps.InputCoverageMaskState = ICMS_NONE;
else if (wm_prog_data->post_depth_coverage)
ps.InputCoverageMaskState = ICMS_DEPTH_COVERAGE;
else if (wm_prog_data->inner_coverage &&
vk_conservative_rasterization_mode(rs_info) !=
VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT)
ps.InputCoverageMaskState = ICMS_INNER_CONSERVATIVE;
ps.InputCoverageMaskState = ICMS_DEPTH_COVERAGE;
else
ps.InputCoverageMaskState = ICMS_INNER_CONSERVATIVE;
ps.InputCoverageMaskState = ICMS_NORMAL;
#else
ps.PixelShaderUsesInputCoverageMask = wm_prog_data->uses_sample_mask;
#endif