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intel/ir: Allow representing additional flag subregisters in the IR.

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This allows representing conditional mods and predicates on f1.0-f1.1
at the IR level by adding an extra bit to the flag_subreg
backend_instruction field.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Francisco Jerez
2017-12-12 12:05:02 -08:00
parent 9ec3362e0b
commit cc0fc8b8ac
7 changed files with 24 additions and 14 deletions
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src/intel/compiler/brw_vec4_generator.cpp
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@@ -1517,7 +1517,7 @@ generate_code(struct brw_codegen *p,
brw_set_default_predicate_control(p, inst->predicate);
brw_set_default_predicate_inverse(p, inst->predicate_inverse);
brw_set_default_flag_reg(p, 0, inst->flag_subreg);
brw_set_default_flag_reg(p, inst->flag_subreg / 2, inst->flag_subreg % 2);
brw_set_default_saturate(p, inst->saturate);
brw_set_default_mask_control(p, inst->force_writemask_all);
brw_set_default_acc_write_control(p, inst->writes_accumulator);