intel/ir: Allow representing additional flag subregisters in the IR.
This allows representing conditional mods and predicates on f1.0-f1.1 at the IR level by adding an extra bit to the flag_subreg backend_instruction field. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
@@ -5488,9 +5488,10 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
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fs_inst *inst = (fs_inst *)be_inst;
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if (inst->predicate) {
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fprintf(file, "(%cf0.%d) ",
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inst->predicate_inverse ? '-' : '+',
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inst->flag_subreg);
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fprintf(file, "(%cf%d.%d) ",
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inst->predicate_inverse ? '-' : '+',
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inst->flag_subreg / 2,
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inst->flag_subreg % 2);
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}
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fprintf(file, "%s", brw_instruction_name(devinfo, inst->opcode));
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@@ -5502,7 +5503,8 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
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(devinfo->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
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inst->opcode != BRW_OPCODE_IF &&
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inst->opcode != BRW_OPCODE_WHILE))) {
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fprintf(file, ".f0.%d", inst->flag_subreg);
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fprintf(file, ".f%d.%d", inst->flag_subreg / 2,
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inst->flag_subreg % 2);
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}
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}
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fprintf(file, "(%d) ", inst->exec_size);
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@@ -5888,7 +5890,7 @@ fs_visitor::calculate_register_pressure()
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bool
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fs_visitor::opt_drop_redundant_mov_to_flags()
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{
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bool flag_mov_found[2] = {false};
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bool flag_mov_found[4] = {false};
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bool progress = false;
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/* Instructions removed by this pass can only be added if this were true */
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@@ -1508,7 +1508,7 @@ fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
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void
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fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
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{
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struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
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struct brw_reg flags = brw_flag_subreg(inst->flag_subreg);
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struct brw_reg dispatch_mask;
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if (devinfo->gen >= 6)
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@@ -1764,7 +1764,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
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brw_set_default_access_mode(p, BRW_ALIGN_1);
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brw_set_default_predicate_control(p, inst->predicate);
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brw_set_default_predicate_inverse(p, inst->predicate_inverse);
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brw_set_default_flag_reg(p, 0, inst->flag_subreg);
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brw_set_default_flag_reg(p, inst->flag_subreg / 2, inst->flag_subreg % 2);
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brw_set_default_saturate(p, inst->saturate);
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brw_set_default_mask_control(p, inst->force_writemask_all);
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brw_set_default_acc_write_control(p, inst->writes_accumulator);
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@@ -842,6 +842,13 @@ brw_flag_reg(int reg, int subreg)
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BRW_ARF_FLAG + reg, subreg);
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}
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static inline struct brw_reg
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brw_flag_subreg(unsigned subreg)
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{
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return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
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BRW_ARF_FLAG + subreg / 2, subreg % 2);
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}
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/**
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* Return the mask register present in Gen4-5, or the related register present
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* in Gen7.5 and later hardware referred to as "channel enable" register in
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@@ -974,7 +974,7 @@ fs_instruction_scheduler::calculate_deps()
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*/
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schedule_node *last_grf_write[grf_count * 16];
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schedule_node *last_mrf_write[BRW_MAX_MRF(v->devinfo->gen)];
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schedule_node *last_conditional_mod[4] = {};
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schedule_node *last_conditional_mod[8] = {};
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schedule_node *last_accumulator_write = NULL;
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/* Fixed HW registers are assumed to be separate from the virtual
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* GRFs, so they can be tracked separately. We don't really write
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@@ -169,10 +169,10 @@ struct backend_instruction {
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bool shadow_compare:1;
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bool eot:1;
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/* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
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/* Chooses which flag subregister (f0.0 to f1.1) is used for conditional
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* mod and predication.
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*/
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unsigned flag_subreg:1;
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unsigned flag_subreg:2;
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/** The number of hardware registers used for a message header. */
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uint8_t header_size;
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@@ -1542,9 +1542,10 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
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vec4_instruction *inst = (vec4_instruction *)be_inst;
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if (inst->predicate) {
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fprintf(file, "(%cf0.%d%s) ",
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fprintf(file, "(%cf%d.%d%s) ",
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inst->predicate_inverse ? '-' : '+',
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inst->flag_subreg,
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inst->flag_subreg / 2,
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inst->flag_subreg % 2,
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pred_ctrl_align16[inst->predicate]);
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}
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@@ -1558,7 +1559,7 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
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(devinfo->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
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inst->opcode != BRW_OPCODE_IF &&
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inst->opcode != BRW_OPCODE_WHILE))) {
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fprintf(file, ".f0.%d", inst->flag_subreg);
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fprintf(file, ".f%d.%d", inst->flag_subreg / 2, inst->flag_subreg % 2);
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}
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}
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fprintf(file, " ");
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@@ -1517,7 +1517,7 @@ generate_code(struct brw_codegen *p,
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brw_set_default_predicate_control(p, inst->predicate);
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brw_set_default_predicate_inverse(p, inst->predicate_inverse);
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brw_set_default_flag_reg(p, 0, inst->flag_subreg);
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brw_set_default_flag_reg(p, inst->flag_subreg / 2, inst->flag_subreg % 2);
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brw_set_default_saturate(p, inst->saturate);
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brw_set_default_mask_control(p, inst->force_writemask_all);
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brw_set_default_acc_write_control(p, inst->writes_accumulator);
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