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intel/ir: Allow representing additional flag subregisters in the IR.

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This allows representing conditional mods and predicates on f1.0-f1.1
at the IR level by adding an extra bit to the flag_subreg
backend_instruction field.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Francisco Jerez
2017-12-12 12:05:02 -08:00
parent 9ec3362e0b
commit cc0fc8b8ac
7 changed files with 24 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/intel/compiler/brw_fs.cpp
View File

@@ -5488,9 +5488,10 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
fs_inst *inst = (fs_inst *)be_inst;
if (inst->predicate) {
fprintf(file, "(%cf0.%d) ",
inst->predicate_inverse ? '-' : '+',
inst->flag_subreg);
fprintf(file, "(%cf%d.%d) ",
inst->predicate_inverse ? '-' : '+',
inst->flag_subreg / 2,
inst->flag_subreg % 2);
}
fprintf(file, "%s", brw_instruction_name(devinfo, inst->opcode));
@@ -5502,7 +5503,8 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
(devinfo->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
inst->opcode != BRW_OPCODE_IF &&
inst->opcode != BRW_OPCODE_WHILE))) {
fprintf(file, ".f0.%d", inst->flag_subreg);
fprintf(file, ".f%d.%d", inst->flag_subreg / 2,
inst->flag_subreg % 2);
}
}
fprintf(file, "(%d) ", inst->exec_size);
@@ -5888,7 +5890,7 @@ fs_visitor::calculate_register_pressure()
bool
fs_visitor::opt_drop_redundant_mov_to_flags()
{
bool flag_mov_found[2] = {false};
bool flag_mov_found[4] = {false};
bool progress = false;
/* Instructions removed by this pass can only be added if this were true */

4
src/intel/compiler/brw_fs_generator.cpp
View File

@@ -1508,7 +1508,7 @@ fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
void
fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
{
struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
struct brw_reg flags = brw_flag_subreg(inst->flag_subreg);
struct brw_reg dispatch_mask;
if (devinfo->gen >= 6)
@@ -1764,7 +1764,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
brw_set_default_access_mode(p, BRW_ALIGN_1);
brw_set_default_predicate_control(p, inst->predicate);
brw_set_default_predicate_inverse(p, inst->predicate_inverse);
brw_set_default_flag_reg(p, 0, inst->flag_subreg);
brw_set_default_flag_reg(p, inst->flag_subreg / 2, inst->flag_subreg % 2);
brw_set_default_saturate(p, inst->saturate);
brw_set_default_mask_control(p, inst->force_writemask_all);
brw_set_default_acc_write_control(p, inst->writes_accumulator);

7
src/intel/compiler/brw_reg.h
View File

@@ -842,6 +842,13 @@ brw_flag_reg(int reg, int subreg)
BRW_ARF_FLAG + reg, subreg);
}
static inline struct brw_reg
brw_flag_subreg(unsigned subreg)
{
return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
BRW_ARF_FLAG + subreg / 2, subreg % 2);
}
/**
* Return the mask register present in Gen4-5, or the related register present
* in Gen7.5 and later hardware referred to as "channel enable" register in

2
src/intel/compiler/brw_schedule_instructions.cpp
View File

@@ -974,7 +974,7 @@ fs_instruction_scheduler::calculate_deps()
*/
schedule_node *last_grf_write[grf_count * 16];
schedule_node *last_mrf_write[BRW_MAX_MRF(v->devinfo->gen)];
schedule_node *last_conditional_mod[4] = {};
schedule_node *last_conditional_mod[8] = {};
schedule_node *last_accumulator_write = NULL;
/* Fixed HW registers are assumed to be separate from the virtual
* GRFs, so they can be tracked separately. We don't really write

4
src/intel/compiler/brw_shader.h
View File

@@ -169,10 +169,10 @@ struct backend_instruction {
bool shadow_compare:1;
bool eot:1;
/* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
/* Chooses which flag subregister (f0.0 to f1.1) is used for conditional
* mod and predication.
*/
unsigned flag_subreg:1;
unsigned flag_subreg:2;
/** The number of hardware registers used for a message header. */
uint8_t header_size;

7
src/intel/compiler/brw_vec4.cpp
View File

@@ -1542,9 +1542,10 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
vec4_instruction *inst = (vec4_instruction *)be_inst;
if (inst->predicate) {
fprintf(file, "(%cf0.%d%s) ",
fprintf(file, "(%cf%d.%d%s) ",
inst->predicate_inverse ? '-' : '+',
inst->flag_subreg,
inst->flag_subreg / 2,
inst->flag_subreg % 2,
pred_ctrl_align16[inst->predicate]);
}
@@ -1558,7 +1559,7 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
(devinfo->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
inst->opcode != BRW_OPCODE_IF &&
inst->opcode != BRW_OPCODE_WHILE))) {
fprintf(file, ".f0.%d", inst->flag_subreg);
fprintf(file, ".f%d.%d", inst->flag_subreg / 2, inst->flag_subreg % 2);
}
}
fprintf(file, " ");

2
src/intel/compiler/brw_vec4_generator.cpp
View File

@@ -1517,7 +1517,7 @@ generate_code(struct brw_codegen *p,
brw_set_default_predicate_control(p, inst->predicate);
brw_set_default_predicate_inverse(p, inst->predicate_inverse);
brw_set_default_flag_reg(p, 0, inst->flag_subreg);
brw_set_default_flag_reg(p, inst->flag_subreg / 2, inst->flag_subreg % 2);
brw_set_default_saturate(p, inst->saturate);
brw_set_default_mask_control(p, inst->force_writemask_all);
brw_set_default_acc_write_control(p, inst->writes_accumulator);