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radv: use vk_image::samples instead of radv_image::info::samples

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22816>
This commit is contained in:
Samuel Pitoiset
2023-05-03 08:28:44 +02:00
committed by Marge Bot
parent d37b020428
commit cb721d5de5
17 changed files with 54 additions and 54 deletions
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6
src/amd/vulkan/meta/radv_meta_blit.c
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@@ -205,7 +205,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
uint32_t dst_width = radv_minify(dst_iview->image->info.width, dst_iview->vk.base_mip_level);
uint32_t dst_height = radv_minify(dst_iview->image->info.height, dst_iview->vk.base_mip_level);
assert(src_image->info.samples == dst_image->info.samples);
assert(src_image->vk.samples == dst_image->vk.samples);
float vertex_push_constants[5] = {
src_offset_0[0] / (float)src_width, src_offset_0[1] / (float)src_height,
@@ -409,8 +409,8 @@ blit_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
* vkCmdBlitImage must not be used for multisampled source or
* destination images. Use vkCmdResolveImage for this purpose.
*/
assert(src_image->info.samples == 1);
assert(dst_image->info.samples == 1);
assert(src_image->vk.samples == 1);
assert(dst_image->vk.samples == 1);
radv_CreateSampler(radv_device_to_handle(device),
&(VkSamplerCreateInfo){

2
src/amd/vulkan/meta/radv_meta_blit2d.c
View File

@@ -382,7 +382,7 @@ radv_meta_blit2d(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_sur
: use_3d ? BLIT2D_SRC_TYPE_IMAGE_3D
: BLIT2D_SRC_TYPE_IMAGE;
radv_meta_blit2d_normal_dst(cmd_buffer, src_img, src_buf, dst, num_rects, rects, src_type,
src_img ? util_logbase2(src_img->image->info.samples) : 0);
src_img ? util_logbase2(src_img->image->vk.samples) : 0);
}
static nir_shader *

4
src/amd/vulkan/meta/radv_meta_bufimage.c
View File

@@ -1665,7 +1665,7 @@ radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta
{
struct radv_device *device = cmd_buffer->device;
struct radv_image_view src_view, dst_view;
uint32_t samples = src->image->info.samples;
uint32_t samples = src->image->vk.samples;
uint32_t samples_log2 = ffs(samples) - 1;
if (src->format == VK_FORMAT_R32G32B32_UINT || src->format == VK_FORMAT_R32G32B32_SINT ||
@@ -1803,7 +1803,7 @@ radv_meta_clear_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_bl
{
struct radv_device *device = cmd_buffer->device;
struct radv_image_view dst_iview;
uint32_t samples = dst->image->info.samples;
uint32_t samples = dst->image->vk.samples;
uint32_t samples_log2 = ffs(samples) - 1;
if (dst->format == VK_FORMAT_R32G32B32_UINT || dst->format == VK_FORMAT_R32G32B32_SINT ||

8
src/amd/vulkan/meta/radv_meta_clear.c
View File

@@ -332,7 +332,7 @@ emit_color_clear(struct radv_cmd_buffer *cmd_buffer, const VkClearAttachment *cl
* the render pass because it's likely a secondary command buffer.
*/
if (color_att->iview) {
samples = color_att->iview->image->info.samples;
samples = color_att->iview->image->vk.samples;
format = color_att->iview->vk.format;
} else {
samples = render->max_samples;
@@ -579,7 +579,7 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer, const VkClearAttachm
*/
struct radv_image_view *iview = render->ds_att.iview;
if (iview) {
samples = iview->image->info.samples;
samples = iview->image->vk.samples;
} else {
assert(render->ds_att.format != VK_FORMAT_UNDEFINED);
samples = render->max_samples;
@@ -1214,7 +1214,7 @@ radv_get_cmask_fast_clear_value(const struct radv_image *image)
*/
if (radv_image_has_dcc(image)) {
/* DCC fast clear with MSAA should clear CMASK to 0xC. */
return image->info.samples > 1 ? 0xcccccccc : 0xffffffff;
return image->vk.samples > 1 ? 0xcccccccc : 0xffffffff;
}
return value;
@@ -1321,7 +1321,7 @@ radv_clear_dcc_comp_to_single(struct radv_cmd_buffer *cmd_buffer,
unsigned bytes_per_pixel = vk_format_get_blocksize(image->vk.format);
unsigned layer_count = vk_image_subresource_layer_count(&image->vk, range);
struct radv_meta_saved_state saved_state;
bool is_msaa = image->info.samples > 1;
bool is_msaa = image->vk.samples > 1;
struct radv_image_view iview;
VkFormat format;

4
src/amd/vulkan/meta/radv_meta_copy.c
View File

@@ -99,7 +99,7 @@ copy_buffer_to_image(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buf
/* The Vulkan 1.0 spec says "dstImage must have a sample count equal to
* VK_SAMPLE_COUNT_1_BIT."
*/
assert(image->info.samples == 1);
assert(image->vk.samples == 1);
cs = cmd_buffer->qf == RADV_QUEUE_COMPUTE ||
!radv_image_is_renderable(cmd_buffer->device, image);
@@ -367,7 +367,7 @@ copy_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
* vkCmdCopyImage can be used to copy image data between multisample
* images, but both images must have the same number of samples.
*/
assert(src_image->info.samples == dst_image->info.samples);
assert(src_image->vk.samples == dst_image->vk.samples);
cs = cmd_buffer->qf == RADV_QUEUE_COMPUTE ||
!radv_image_is_renderable(cmd_buffer->device, dst_image);

2
src/amd/vulkan/meta/radv_meta_decompress.c
View File

@@ -358,7 +358,7 @@ radv_get_depth_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_image *i
const VkImageSubresourceRange *subresourceRange, enum radv_depth_op op)
{
struct radv_meta_state *state = &cmd_buffer->device->meta_state;
uint32_t samples = image->info.samples;
uint32_t samples = image->vk.samples;
uint32_t samples_log2 = ffs(samples) - 1;
VkPipeline *pipeline;

2
src/amd/vulkan/meta/radv_meta_fmask_copy.c
View File

@@ -286,7 +286,7 @@ radv_fmask_copy(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf
{
struct radv_device *device = cmd_buffer->device;
struct radv_image_view src_iview, dst_iview;
uint32_t samples = src->image->info.samples;
uint32_t samples = src->image->vk.samples;
uint32_t samples_log2 = ffs(samples) - 1;
VkResult result = radv_device_init_meta_fmask_copy_state_internal(device, samples_log2);

2
src/amd/vulkan/meta/radv_meta_fmask_expand.c
View File

@@ -78,7 +78,7 @@ radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer, struct radv_
{
struct radv_device *device = cmd_buffer->device;
struct radv_meta_saved_state saved_state;
const uint32_t samples = image->info.samples;
const uint32_t samples = image->vk.samples;
const uint32_t samples_log2 = ffs(samples) - 1;
unsigned layer_count = vk_image_subresource_layer_count(&image->vk, subresourceRange);
struct radv_image_view iview;

4
src/amd/vulkan/meta/radv_meta_resolve.c
View File

@@ -347,8 +347,8 @@ radv_meta_resolve_hardware_image(struct radv_cmd_buffer *cmd_buffer, struct radv
radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_GRAPHICS_PIPELINE);
assert(src_image->info.samples > 1);
assert(dst_image->info.samples == 1);
assert(src_image->vk.samples > 1);
assert(dst_image->vk.samples == 1);
unsigned fs_key = radv_format_meta_fs_key(device, dst_image->vk.format);

4
src/amd/vulkan/meta/radv_meta_resolve_cs.c
View File

@@ -460,7 +460,7 @@ radv_get_resolve_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_image_
{
struct radv_device *device = cmd_buffer->device;
struct radv_meta_state *state = &device->meta_state;
uint32_t samples = src_iview->image->info.samples;
uint32_t samples = src_iview->image->vk.samples;
uint32_t samples_log2 = ffs(samples) - 1;
VkPipeline *pipeline;
@@ -545,7 +545,7 @@ emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image
VkResolveModeFlagBits resolve_mode)
{
struct radv_device *device = cmd_buffer->device;
const uint32_t samples = src_iview->image->info.samples;
const uint32_t samples = src_iview->image->vk.samples;
const uint32_t samples_log2 = ffs(samples) - 1;
VkPipeline *pipeline;

4
src/amd/vulkan/meta/radv_meta_resolve_fs.c
View File

@@ -582,7 +582,7 @@ radv_get_resolve_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_image_
{
struct radv_device *device = cmd_buffer->device;
unsigned fs_key = radv_format_meta_fs_key(cmd_buffer->device, dst_iview->vk.format);
const uint32_t samples = src_iview->image->info.samples;
const uint32_t samples = src_iview->image->vk.samples;
const uint32_t samples_log2 = ffs(samples) - 1;
VkPipeline *pipeline;
@@ -657,7 +657,7 @@ emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image
VkResolveModeFlagBits resolve_mode)
{
struct radv_device *device = cmd_buffer->device;
const uint32_t samples = src_iview->image->info.samples;
const uint32_t samples = src_iview->image->vk.samples;
const uint32_t samples_log2 = ffs(samples) - 1;
VkPipeline *pipeline;

4
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -10185,7 +10185,7 @@ radv_init_fmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
const VkImageSubresourceRange *range)
{
static const uint32_t fmask_clear_values[4] = {0x00000000, 0x02020202, 0xE4E4E4E4, 0x76543210};
uint32_t log2_samples = util_logbase2(image->info.samples);
uint32_t log2_samples = util_logbase2(image->vk.samples);
uint32_t value = fmask_clear_values[log2_samples];
struct radv_barrier_data barrier = {0};
@@ -10270,7 +10270,7 @@ radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_i
}
} else {
static const uint32_t cmask_clear_values[4] = {0xffffffff, 0xdddddddd, 0xeeeeeeee, 0xffffffff};
uint32_t log2_samples = util_logbase2(image->info.samples);
uint32_t log2_samples = util_logbase2(image->vk.samples);
value = cmask_clear_values[log2_samples];
}

22
src/amd/vulkan/radv_device.c
View File

@@ -1368,7 +1368,7 @@ static unsigned
get_dcc_max_uncompressed_block_size(const struct radv_device *device,
const struct radv_image_view *iview)
{
if (device->physical_device->rad_info.gfx_level < GFX10 && iview->image->info.samples > 1) {
if (device->physical_device->rad_info.gfx_level < GFX10 && iview->image->vk.samples > 1) {
if (iview->image->planes[0].surface.bpe == 1)
return V_028C78_MAX_BLOCK_SIZE_64B;
else if (iview->image->planes[0].surface.bpe == 2)
@@ -1564,8 +1564,8 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
uint32_t slice_start = iview->nbc_view.valid ? 0 : iview->vk.base_array_layer;
cb->cb_color_view = S_028C6C_SLICE_START(slice_start) | S_028C6C_SLICE_MAX_GFX10(max_slice);
if (iview->image->info.samples > 1) {
unsigned log_samples = util_logbase2(iview->image->info.samples);
if (iview->image->vk.samples > 1) {
unsigned log_samples = util_logbase2(iview->image->vk.samples);
if (device->physical_device->rad_info.gfx_level >= GFX11)
cb->cb_color_attrib |= S_028C74_NUM_FRAGMENTS_GFX11(log_samples);
@@ -1709,14 +1709,14 @@ radv_calc_decompress_on_z_planes(struct radv_device *device, struct radv_image_v
/* Default value for 32-bit depth surfaces. */
max_zplanes = 4;
if (iview->vk.format == VK_FORMAT_D16_UNORM && iview->image->info.samples > 1)
if (iview->vk.format == VK_FORMAT_D16_UNORM && iview->image->vk.samples > 1)
max_zplanes = 2;
/* Workaround for a DB hang when ITERATE_256 is set to 1. Only affects 4X MSAA D/S images. */
if (device->physical_device->rad_info.has_two_planes_iterate256_bug &&
radv_image_get_iterate256(device, iview->image) &&
!radv_image_tile_stencil_disabled(device, iview->image) &&
iview->image->info.samples == 4) {
iview->image->vk.samples == 4) {
max_zplanes = 1;
}
@@ -1731,9 +1731,9 @@ radv_calc_decompress_on_z_planes(struct radv_device *device, struct radv_image_v
*/
max_zplanes = 1;
} else {
if (iview->image->info.samples <= 1)
if (iview->image->vk.samples <= 1)
max_zplanes = 5;
else if (iview->image->info.samples <= 4)
else if (iview->image->vk.samples <= 4)
max_zplanes = 3;
else
max_zplanes = 2;
@@ -1820,7 +1820,7 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf
s_offs = z_offs = va;
/* Recommended value for better performance with 4x and 8x. */
ds->db_render_override2 = S_028010_DECOMPRESS_Z_ON_FLUSH(iview->image->info.samples >= 4) |
ds->db_render_override2 = S_028010_DECOMPRESS_Z_ON_FLUSH(iview->image->vk.samples >= 4) |
S_028010_CENTROID_COMPUTATION_MODE(device->physical_device->rad_info.gfx_level >= GFX10_3);
if (device->physical_device->rad_info.gfx_level >= GFX9) {
@@ -1828,7 +1828,7 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf
s_offs += surf->u.gfx9.zs.stencil_offset;
ds->db_z_info = S_028038_FORMAT(format) |
S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
S_028038_NUM_SAMPLES(util_logbase2(iview->image->vk.samples)) |
S_028038_SW_MODE(surf->u.gfx9.swizzle_mode) |
S_028038_MAXMIP(iview->image->vk.mip_levels - 1) |
S_028038_ZRANGE_PRECISION(1) |
@@ -1897,8 +1897,8 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf
ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
ds->db_stencil_info = S_028044_FORMAT(stencil_format);
if (iview->image->info.samples > 1)
ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
if (iview->image->vk.samples > 1)
ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->vk.samples));
if (device->physical_device->rad_info.gfx_level >= GFX7) {
struct radeon_info *info = &device->physical_device->rad_info;

2
src/amd/vulkan/radv_device_memory.c
View File

@@ -176,7 +176,7 @@ radv_alloc_memory(struct radv_device *device, const VkMemoryAllocateInfo *pAlloc
}
if (mem->image && mem->image->plane_count == 1 &&
!vk_format_is_depth_or_stencil(mem->image->vk.format) && mem->image->info.samples == 1 &&
!vk_format_is_depth_or_stencil(mem->image->vk.format) && mem->image->vk.samples == 1 &&
mem->image->vk.tiling != VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) {
struct radeon_bo_metadata metadata;
device->ws->buffer_get_metadata(device->ws, mem->bo, &metadata);

34
src/amd/vulkan/radv_image.c
View File

@@ -130,7 +130,7 @@ radv_image_use_fast_clear_for_image_early(const struct radv_device *device,
if (device->instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS)
return true;
if (image->info.samples <= 1 && image->info.width * image->info.height <= 512 * 512) {
if (image->vk.samples <= 1 && image->info.width * image->info.height <= 512 * 512) {
/* Do not enable CMASK or DCC for small surfaces where the cost
* of the eliminate pass can be higher than the benefit of fast
* clear. RadeonSI does this, but the image threshold is
@@ -343,7 +343,7 @@ radv_image_use_dcc_predication(const struct radv_device *device, const struct ra
static inline bool
radv_use_fmask_for_image(const struct radv_device *device, const struct radv_image *image)
{
return device->physical_device->use_fmask && image->info.samples > 1 &&
return device->physical_device->use_fmask && image->vk.samples > 1 &&
((image->vk.usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) ||
(device->instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS));
}
@@ -385,7 +385,7 @@ radv_use_tc_compat_cmask_for_image(struct radv_device *device, struct radv_image
/* GFX9 has issues when sample count is greater than 2 */
if (device->physical_device->rad_info.gfx_level == GFX9 &&
image->info.samples > 2)
image->vk.samples > 2)
return false;
if (device->instance->debug_flags & RADV_DEBUG_NO_TC_COMPAT_CMASK)
@@ -1049,7 +1049,7 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima
assert(image->vk.image_type == VK_IMAGE_TYPE_3D);
type = V_008F1C_SQ_RSRC_IMG_3D;
} else {
type = radv_tex_dim(image->vk.image_type, view_type, image->vk.array_layers, image->info.samples,
type = radv_tex_dim(image->vk.image_type, view_type, image->vk.array_layers, image->vk.samples,
is_storage_image, device->physical_device->rad_info.gfx_level == GFX9);
}
@@ -1071,8 +1071,8 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima
S_00A00C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
S_00A00C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
S_00A00C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
S_00A00C_BASE_LEVEL(image->info.samples > 1 ? 0 : first_level) |
S_00A00C_LAST_LEVEL(image->info.samples > 1 ? util_logbase2(image->info.samples)
S_00A00C_BASE_LEVEL(image->vk.samples > 1 ? 0 : first_level) |
S_00A00C_LAST_LEVEL(image->vk.samples > 1 ? util_logbase2(image->vk.samples)
: last_level) |
S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc)) | S_00A00C_TYPE(type);
/* Depth is the the last accessible layer on gfx9+. The hw doesn't need
@@ -1111,7 +1111,7 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima
}
unsigned max_mip =
image->info.samples > 1 ? util_logbase2(image->info.samples) : image->vk.mip_levels - 1;
image->vk.samples > 1 ? util_logbase2(image->vk.samples) : image->vk.mip_levels - 1;
if (nbc_view && nbc_view->valid)
max_mip = nbc_view->num_levels - 1;
@@ -1147,7 +1147,7 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima
va = gpu_address + image->bindings[0].offset + image->planes[0].surface.fmask_offset;
switch (image->info.samples) {
switch (image->vk.samples) {
case 2:
format = V_008F0C_GFX10_FORMAT_FMASK8_S2_F2;
break;
@@ -1247,7 +1247,7 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image,
assert(image->vk.image_type == VK_IMAGE_TYPE_3D);
type = V_008F1C_SQ_RSRC_IMG_3D;
} else {
type = radv_tex_dim(image->vk.image_type, view_type, image->vk.array_layers, image->info.samples,
type = radv_tex_dim(image->vk.image_type, view_type, image->vk.array_layers, image->vk.samples,
is_storage_image, device->physical_device->rad_info.gfx_level == GFX9);
}
@@ -1269,8 +1269,8 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image,
S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
S_008F1C_BASE_LEVEL(image->info.samples > 1 ? 0 : first_level) |
S_008F1C_LAST_LEVEL(image->info.samples > 1 ? util_logbase2(image->info.samples)
S_008F1C_BASE_LEVEL(image->vk.samples > 1 ? 0 : first_level) |
S_008F1C_LAST_LEVEL(image->vk.samples > 1 ? util_logbase2(image->vk.samples)
: last_level) |
S_008F1C_TYPE(type));
state[4] = 0;
@@ -1290,7 +1290,7 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image,
state[4] |= S_008F20_DEPTH(last_layer);
state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ? util_logbase2(image->info.samples)
state[5] |= S_008F24_MAX_MIP(image->vk.samples > 1 ? util_logbase2(image->vk.samples)
: image->vk.mip_levels - 1);
} else {
state[3] |= S_008F1C_POW2_PAD(image->vk.mip_levels > 1);
@@ -1305,7 +1305,7 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image,
/* The last dword is unused by hw. The shader uses it to clear
* bits in the first dword of sampler state.
*/
if (device->physical_device->rad_info.gfx_level <= GFX7 && image->info.samples <= 1) {
if (device->physical_device->rad_info.gfx_level <= GFX7 && image->vk.samples <= 1) {
if (first_level == last_level)
state[7] = C_008F30_MAX_ANISO_RATIO;
else
@@ -1327,7 +1327,7 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image,
if (device->physical_device->rad_info.gfx_level == GFX9) {
fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
switch (image->info.samples) {
switch (image->vk.samples) {
case 2:
num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_2_2;
break;
@@ -1341,7 +1341,7 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image,
unreachable("invalid nr_samples");
}
} else {
switch (image->info.samples) {
switch (image->vk.samples) {
case 2:
fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
break;
@@ -1556,7 +1556,7 @@ static bool
radv_image_is_pipe_misaligned(const struct radv_device *device, const struct radv_image *image)
{
struct radeon_info *rad_info = &device->physical_device->rad_info;
int log2_samples = util_logbase2(image->info.samples);
int log2_samples = util_logbase2(image->vk.samples);
assert(rad_info->gfx_level >= GFX10);
@@ -1607,7 +1607,7 @@ radv_image_is_l2_coherent(const struct radv_device *device, const struct radv_im
return !device->physical_device->rad_info.tcc_rb_non_coherent &&
!radv_image_is_pipe_misaligned(device, image);
} else if (device->physical_device->rad_info.gfx_level == GFX9) {
if (image->info.samples == 1 &&
if (image->vk.samples == 1 &&
(image->vk.usage &
(VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT | VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
!vk_format_has_stencil(image->vk.format)) {

2
src/amd/vulkan/radv_private.h
View File

@@ -2792,7 +2792,7 @@ radv_image_get_iterate256(struct radv_device *device, struct radv_image *image)
return device->physical_device->rad_info.gfx_level >= GFX10 &&
(image->vk.usage &
(VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT | VK_IMAGE_USAGE_TRANSFER_DST_BIT)) &&
radv_image_is_tc_compat_htile(image) && image->info.samples > 1;
radv_image_is_tc_compat_htile(image) && image->vk.samples > 1;
}
unsigned radv_image_queue_family_mask(const struct radv_image *image,

2
src/amd/vulkan/radv_rmv.c
View File

@@ -585,7 +585,7 @@ radv_rmv_log_image_create(struct radv_device *device, const VkImageCreateInfo *c
token.image.num_slices = create_info->arrayLayers;
token.image.tiling = create_info->tiling;
token.image.alignment_log2 = util_logbase2(image->alignment);
token.image.log2_samples = util_logbase2(image->info.samples);
token.image.log2_samples = util_logbase2(image->vk.samples);
token.image.log2_storage_samples = util_logbase2(image->vk.samples);
token.image.metadata_alignment_log2 = image->planes[0].surface.meta_alignment_log2;
token.image.image_alignment_log2 = image->planes[0].surface.alignment_log2;