From cb59cae04c32c9ffaedd16e91d96fabbe7c9e3ea Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
Date: Fri, 19 Mar 2021 17:41:59 -0400
Subject: [PATCH] radeonsi: set the clear/copy cache policy based on L2 cache
 size

This matches the intent.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
---
 src/gallium/drivers/radeonsi/si_compute_blit.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c
index 16a8aebd06e..f1b09caaf45 100644
--- a/src/gallium/drivers/radeonsi/si_compute_blit.c
+++ b/src/gallium/drivers/radeonsi/si_compute_blit.c
@@ -37,7 +37,7 @@ static enum si_cache_policy get_cache_policy(struct si_context *sctx, enum si_co
                                      coher == SI_COHERENCY_DB_META ||
                                      coher == SI_COHERENCY_CP)) ||
        (sctx->chip_class >= GFX7 && coher == SI_COHERENCY_SHADER))
-      return size <= 256 * 1024 ? L2_LRU : L2_STREAM;
+      return size <= sctx->screen->info.l2_cache_size / 8 ? L2_LRU : L2_STREAM;
 
    return L2_BYPASS;
 }