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i965: Add functions to abstract access to register types

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Previously the brw_inst{,_set}_{dst,src0,src1}_reg_type() functions
provided access to the hardware encodings for the register types. We
often mixed these with the logical BRW_REGISTER_TYPE_* enums (which
themselves used to be the hardware format!) with bad results.

With that functionality now available with the hw_ versions (see
previous commit), we now add functions that take the logical
BRW_REGISTER_TYPE_* enums and convert into the hardware format and vice
versa. To do the conversion we also have to provide the file.

Note the asymmetry between the two functions: the new getter reads the
file from the instruction word, and to ensure that is always set the
setter writes both the file and the type.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
This commit is contained in:
Matt Turner
2017-07-26 16:51:58 -07:00
parent 9fb8323328
commit cb2cd462b1
2 changed files with 79 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
src/intel/compiler/brw_inst.h
View File

@@ -35,6 +35,7 @@
#include <stdint.h>
#include "brw_eu_defines.h"
#include "brw_reg_type.h"
#include "common/gen_device_info.h"
#ifdef __cplusplus
@@ -652,6 +653,33 @@ brw_inst_set_imm_uq(const struct gen_device_info *devinfo,
/** @} */
#define REG_TYPE(reg) \
static inline void \
brw_inst_set_##reg##_file_type(const struct gen_device_info *devinfo, \
brw_inst *inst, enum brw_reg_file file, \
enum brw_reg_type type) \
{ \
assert(file <= BRW_IMMEDIATE_VALUE); \
unsigned hw_type = brw_reg_type_to_hw_type(devinfo, file, type); \
brw_inst_set_##reg##_reg_file(devinfo, inst, file); \
brw_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \
} \
\
static inline enum brw_reg_type \
brw_inst_##reg##_type(const struct gen_device_info *devinfo, \
const brw_inst *inst) \
{ \
unsigned file = brw_inst_##reg##_reg_file(devinfo, inst); \
unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst); \
return brw_hw_type_to_reg_type(devinfo, (enum brw_reg_file)file, hw_type); \
}
REG_TYPE(dst)
REG_TYPE(src0)
REG_TYPE(src1)
#undef REG_TYPE
/* The AddrImm fields are split into two discontiguous sections on Gen8+ */
#define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
static inline void \

102
src/intel/compiler/test_eu_validate.cpp
View File

@@ -208,19 +208,19 @@ TEST_P(validation_test, opcode46)
TEST_P(validation_test, dest_stride_must_be_equal_to_the_ratio_of_exec_size_to_dest_size)
{
brw_ADD(p, g0, g0, g0);
brw_inst_set_dst_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src0_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_D);
brw_inst_set_src1_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_D);
brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D);
brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D);
EXPECT_FALSE(validate(p));
clear_instructions(p);
brw_ADD(p, g0, g0, g0);
brw_inst_set_dst_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
brw_inst_set_src0_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_D);
brw_inst_set_src1_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_D);
brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D);
brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D);
EXPECT_TRUE(validate(p));
}
@@ -234,9 +234,9 @@ TEST_P(validation_test, dst_subreg_must_be_aligned_to_exec_type_size)
brw_ADD(p, g0, g0, g0);
brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 2);
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
brw_inst_set_dst_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src0_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_D);
brw_inst_set_src1_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_D);
brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D);
brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D);
EXPECT_FALSE(validate(p));
@@ -246,12 +246,12 @@ TEST_P(validation_test, dst_subreg_must_be_aligned_to_exec_type_size)
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_4);
brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 8);
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
brw_inst_set_dst_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src0_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_D);
brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D);
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
brw_inst_set_src1_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_D);
brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D);
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
@@ -379,8 +379,8 @@ TEST_P(validation_test, dst_horizontal_stride_0)
EXPECT_FALSE(validate(p));
}
/* VertStride must be used to cross GRF register boundaries. This rule implies
* that elements within a 'Width' cannot cross GRF boundaries.
/* VertStride must be used to cross BRW_GENERAL_REGISTER_FILE register boundaries. This rule implies
* that elements within a 'Width' cannot cross BRW_GENERAL_REGISTER_FILE boundaries.
*/
TEST_P(validation_test, must_not_cross_grf_boundary_in_a_width)
{
@@ -471,16 +471,16 @@ TEST_P(validation_test, vstride_on_align16_must_be_0_or_4)
}
}
/* In Direct Addressing mode, a source cannot span more than 2 adjacent GRF
/* In Direct Addressing mode, a source cannot span more than 2 adjacent BRW_GENERAL_REGISTER_FILE
* registers.
*/
TEST_P(validation_test, source_cannot_span_more_than_2_registers)
{
brw_ADD(p, g0, g0, g0);
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_32);
brw_inst_set_dst_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src0_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src1_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_8);
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
@@ -491,9 +491,9 @@ TEST_P(validation_test, source_cannot_span_more_than_2_registers)
brw_ADD(p, g0, g0, g0);
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
brw_inst_set_dst_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src0_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src1_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_8);
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
@@ -509,15 +509,15 @@ TEST_P(validation_test, source_cannot_span_more_than_2_registers)
EXPECT_TRUE(validate(p));
}
/* A destination cannot span more than 2 adjacent GRF registers. */
/* A destination cannot span more than 2 adjacent BRW_GENERAL_REGISTER_FILE registers. */
TEST_P(validation_test, destination_cannot_span_more_than_2_registers)
{
brw_ADD(p, g0, g0, g0);
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_32);
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
brw_inst_set_dst_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src0_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src1_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
EXPECT_FALSE(validate(p));
@@ -527,12 +527,12 @@ TEST_P(validation_test, destination_cannot_span_more_than_2_registers)
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_8);
brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 6);
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_4);
brw_inst_set_dst_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src0_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
brw_inst_set_src1_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
@@ -544,9 +544,9 @@ TEST_P(validation_test, src_region_spans_two_regs_dst_region_spans_one)
{
/* Writes to dest are to the lower OWord */
brw_ADD(p, g0, g0, g0);
brw_inst_set_dst_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src0_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src1_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
@@ -558,9 +558,9 @@ TEST_P(validation_test, src_region_spans_two_regs_dst_region_spans_one)
/* Writes to dest are to the upper OWord */
brw_ADD(p, g0, g0, g0);
brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 16);
brw_inst_set_dst_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src0_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src1_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
@@ -572,9 +572,9 @@ TEST_P(validation_test, src_region_spans_two_regs_dst_region_spans_one)
/* Writes to dest are evenly split between OWords */
brw_ADD(p, g0, g0, g0);
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
brw_inst_set_dst_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src0_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src1_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_8);
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
@@ -587,12 +587,12 @@ TEST_P(validation_test, src_region_spans_two_regs_dst_region_spans_one)
brw_ADD(p, g0, g0, g0);
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_4);
brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 10);
brw_inst_set_dst_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src0_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
brw_inst_set_src1_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_2);
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
@@ -679,9 +679,9 @@ TEST_P(validation_test, two_src_two_dst_each_dst_must_be_derived_from_one_src)
brw_MOV(p, g0, g0);
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
brw_inst_set_dst_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
brw_inst_set_src0_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, 8);
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
@@ -716,9 +716,9 @@ TEST_P(validation_test, one_src_two_dst)
brw_ADD(p, g0, g0, g0);
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
brw_inst_set_dst_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_D);
brw_inst_set_src0_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src1_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_D);
brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
EXPECT_TRUE(validate(p));
@@ -727,9 +727,9 @@ TEST_P(validation_test, one_src_two_dst)
brw_ADD(p, g0, g0, g0);
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
brw_inst_set_dst_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src0_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src1_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_1);
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
@@ -745,12 +745,12 @@ TEST_P(validation_test, one_src_two_dst)
brw_ADD(p, g0, g0, g0);
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
brw_inst_set_dst_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src0_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1);
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
brw_inst_set_src1_reg_hw_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
if (devinfo.gen >= 8) {
EXPECT_TRUE(validate(p));