intel/blorp: Add a partial resolve pass for MCS
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
@@ -205,6 +205,12 @@ blorp_ccs_resolve_attachment(struct blorp_batch *batch,
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const enum isl_format format,
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const enum blorp_fast_clear_op resolve_op);
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void
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blorp_mcs_partial_resolve(struct blorp_batch *batch,
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struct blorp_surf *surf,
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enum isl_format format,
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uint32_t start_layer, uint32_t num_layers);
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/**
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* For an overview of the HiZ operations, see the following sections of the
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* Sandy Bridge PRM, Volume 1, Part2:
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@@ -29,7 +29,7 @@
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#include "blorp_priv.h"
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#include "compiler/brw_eu_defines.h"
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#include "compiler/nir/nir_builder.h"
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#include "blorp_nir_builder.h"
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#define FILE_DEBUG_FLAG DEBUG_BLORP
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@@ -794,3 +794,106 @@ blorp_ccs_resolve_attachment(struct blorp_batch *batch,
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batch->blorp->exec(batch, ¶ms);
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}
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struct blorp_mcs_partial_resolve_key
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{
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enum blorp_shader_type shader_type;
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uint32_t num_samples;
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};
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static bool
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blorp_params_get_mcs_partial_resolve_kernel(struct blorp_context *blorp,
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struct blorp_params *params)
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{
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const struct blorp_mcs_partial_resolve_key blorp_key = {
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.shader_type = BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE,
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.num_samples = params->num_samples,
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};
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if (blorp->lookup_shader(blorp, &blorp_key, sizeof(blorp_key),
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¶ms->wm_prog_kernel, ¶ms->wm_prog_data))
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return true;
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void *mem_ctx = ralloc_context(NULL);
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nir_builder b;
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nir_builder_init_simple_shader(&b, mem_ctx, MESA_SHADER_FRAGMENT, NULL);
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b.shader->info.name = ralloc_strdup(b.shader, "BLORP-mcs-partial-resolve");
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nir_variable *v_color =
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BLORP_CREATE_NIR_INPUT(b.shader, clear_color, glsl_vec4_type());
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nir_variable *frag_color =
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nir_variable_create(b.shader, nir_var_shader_out,
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glsl_vec4_type(), "gl_FragColor");
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frag_color->data.location = FRAG_RESULT_COLOR;
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/* Do an MCS fetch and check if it is equal to the magic clear value */
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nir_ssa_def *mcs =
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blorp_nir_txf_ms_mcs(&b, nir_f2i32(&b, blorp_nir_frag_coord(&b)),
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nir_load_layer_id(&b));
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nir_ssa_def *is_clear =
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blorp_nir_mcs_is_clear_color(&b, mcs, blorp_key.num_samples);
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/* If we aren't the clear value, discard. */
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nir_intrinsic_instr *discard =
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nir_intrinsic_instr_create(b.shader, nir_intrinsic_discard_if);
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discard->src[0] = nir_src_for_ssa(nir_inot(&b, is_clear));
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nir_builder_instr_insert(&b, &discard->instr);
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nir_copy_var(&b, frag_color, v_color);
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struct brw_wm_prog_key wm_key;
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brw_blorp_init_wm_prog_key(&wm_key);
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wm_key.tex.compressed_multisample_layout_mask = 1;
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wm_key.tex.msaa_16 = blorp_key.num_samples == 16;
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wm_key.multisample_fbo = true;
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struct brw_wm_prog_data prog_data;
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unsigned program_size;
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const unsigned *program =
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blorp_compile_fs(blorp, mem_ctx, b.shader, &wm_key, false,
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&prog_data, &program_size);
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bool result =
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blorp->upload_shader(blorp, &blorp_key, sizeof(blorp_key),
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program, program_size,
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&prog_data.base, sizeof(prog_data),
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¶ms->wm_prog_kernel, ¶ms->wm_prog_data);
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ralloc_free(mem_ctx);
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return result;
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}
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void
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blorp_mcs_partial_resolve(struct blorp_batch *batch,
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struct blorp_surf *surf,
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enum isl_format format,
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uint32_t start_layer, uint32_t num_layers)
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{
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struct blorp_params params;
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blorp_params_init(¶ms);
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assert(batch->blorp->isl_dev->info->gen >= 7);
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params.x0 = 0;
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params.y0 = 0;
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params.x1 = surf->surf->logical_level0_px.width;
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params.y1 = surf->surf->logical_level0_px.height;
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brw_blorp_surface_info_init(batch->blorp, ¶ms.src, surf, 0,
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start_layer, format, false);
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brw_blorp_surface_info_init(batch->blorp, ¶ms.dst, surf, 0,
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start_layer, format, true);
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params.num_samples = params.dst.surf.samples;
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params.num_layers = num_layers;
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memcpy(¶ms.wm_inputs.clear_color,
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surf->clear_color.f32, sizeof(float) * 4);
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if (!blorp_params_get_mcs_partial_resolve_kernel(batch->blorp, ¶ms))
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return;
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batch->blorp->exec(batch, ¶ms);
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}
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102
src/intel/blorp/blorp_nir_builder.h
Normal file
102
src/intel/blorp/blorp_nir_builder.h
Normal file
@@ -0,0 +1,102 @@
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/*
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* Copyright © 2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "compiler/nir/nir_builder.h"
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static inline nir_ssa_def *
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blorp_nir_frag_coord(nir_builder *b)
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{
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nir_variable *frag_coord =
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nir_variable_create(b->shader, nir_var_shader_in,
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glsl_vec4_type(), "gl_FragCoord");
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frag_coord->data.location = VARYING_SLOT_POS;
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frag_coord->data.origin_upper_left = true;
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return nir_load_var(b, frag_coord);
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}
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static inline nir_ssa_def *
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blorp_nir_txf_ms_mcs(nir_builder *b, nir_ssa_def *xy_pos, nir_ssa_def *layer)
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{
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nir_tex_instr *tex = nir_tex_instr_create(b->shader, 1);
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tex->op = nir_texop_txf_ms_mcs;
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tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
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tex->dest_type = nir_type_int;
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nir_ssa_def *coord;
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if (layer) {
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tex->is_array = true;
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tex->coord_components = 3;
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coord = nir_vec3(b, nir_channel(b, xy_pos, 0),
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nir_channel(b, xy_pos, 1),
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layer);
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} else {
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tex->is_array = false;
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tex->coord_components = 2;
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coord = nir_channels(b, xy_pos, 0x3);
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}
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tex->src[0].src_type = nir_tex_src_coord;
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tex->src[0].src = nir_src_for_ssa(coord);
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/* Blorp only has one texture and it's bound at unit 0 */
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tex->texture_index = 0;
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tex->sampler_index = 0;
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nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, NULL);
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nir_builder_instr_insert(b, &tex->instr);
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return &tex->dest.ssa;
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}
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static inline nir_ssa_def *
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blorp_nir_mcs_is_clear_color(nir_builder *b,
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nir_ssa_def *mcs,
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uint32_t samples)
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{
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switch (samples) {
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case 2:
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/* Empirical evidence suggests that the value returned from the
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* sampler is not always 0x3 for clear color so we need to mask it.
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*/
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return nir_ieq(b, nir_iand(b, nir_channel(b, mcs, 0),
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nir_imm_int(b, 0x3)),
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nir_imm_int(b, 0x3));
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case 4:
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return nir_ieq(b, nir_channel(b, mcs, 0), nir_imm_int(b, 0xff));
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case 8:
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return nir_ieq(b, nir_channel(b, mcs, 0), nir_imm_int(b, ~0));
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case 16:
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/* For 16x MSAA, the MCS is actually an ivec2 */
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return nir_iand(b, nir_ieq(b, nir_channel(b, mcs, 0),
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nir_imm_int(b, ~0)),
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nir_ieq(b, nir_channel(b, mcs, 1),
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nir_imm_int(b, ~0)));
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default:
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unreachable("Invalid sample count");
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}
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}
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@@ -209,6 +209,7 @@ void blorp_params_init(struct blorp_params *params);
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enum blorp_shader_type {
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BLORP_SHADER_TYPE_BLIT,
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BLORP_SHADER_TYPE_CLEAR,
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BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE,
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BLORP_SHADER_TYPE_LAYER_OFFSET_VS,
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BLORP_SHADER_TYPE_GEN4_SF,
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};
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