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intel/fs: the maximum supported stride width is 16

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There are cases where we try to generate registers with a stride of
32, while the hardware maximum is just 16. This happens, for example,
when using 8 bit integers on SIMD32. This results in a crash because
the variable 'width' has a value of 32:

../../src/intel/compiler/brw_reg.h:550: brw_reg brw_vecn_reg(unsigned
int, brw_reg_file, unsigned int, unsigned int): Assertion `!"Invalid
register width"' failed.

This change prevents the crash and makes the tests pass.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
This commit is contained in:
Paulo Zanoni
2019-08-30 17:16:28 -07:00
committed by Jason Ekstrand
parent cebf447d16
commit c99df52873
1 changed files with 3 additions and 1 deletions
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4
src/intel/compiler/brw_fs_generator.cpp
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@@ -85,6 +85,8 @@ brw_reg_from_fs_reg(const struct gen_device_info *devinfo, fs_inst *inst,
const unsigned phys_width = compressed ? inst->exec_size / 2 :
inst->exec_size;
const unsigned max_hw_width = 16;
/* XXX - The equation above is strictly speaking not correct on
* hardware that supports unbalanced GRF writes -- On Gen9+
* each decompressed chunk of the instruction may have a
@@ -97,7 +99,7 @@ brw_reg_from_fs_reg(const struct gen_device_info *devinfo, fs_inst *inst,
brw_reg = brw_vecn_reg(1, brw_file_from_reg(reg), reg->nr, 0);
brw_reg = stride(brw_reg, reg->stride, 1, 0);
} else {
const unsigned width = MIN2(reg_width, phys_width);
const unsigned width = MIN3(reg_width, phys_width, max_hw_width);
brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg->nr, 0);
brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
}