broadcom/compiler: force a last thrsw for spilling
As we don't know if we are going to have spilling or not, emit always a last thrsw at the end of the shader. If later we don't have spillings and we don't need that last thrsw, we remove it and switch back to the previous one. This way we ensure all the spilling happens always before the last thrsw. v2 (Juan): - Rework the code to force a last thrsw and remove later if no spilling v3: - Merge functionality inside vir_emit_last_thrsw (Iago) - Add vir_restore_last_thrsw (Juan) v4 (Iago): - Fix/add new comments - Rename variables/parameters v5 (Iago): - Fix comments - Add assertion Cc: mesa-stable Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4760 Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12322>
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@@ -261,7 +261,7 @@ v3d_spill_reg(struct v3d_compile *c, int spill_temp)
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}
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struct qinst *last_thrsw = c->last_thrsw;
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assert(!last_thrsw || last_thrsw->is_last_thrsw);
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assert(last_thrsw && last_thrsw->is_last_thrsw);
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int start_num_temps = c->num_temps;
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@@ -347,29 +347,13 @@ v3d_spill_reg(struct v3d_compile *c, int spill_temp)
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spill_offset);
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}
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}
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/* If we didn't have a last-thrsw inserted by nir_to_vir and
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* we've been inserting thrsws, then insert a new last_thrsw
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* right before we start the vpm/tlb sequence for the last
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* thread segment.
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*/
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if (!is_uniform && !last_thrsw && c->last_thrsw &&
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(v3d_qpu_writes_vpm(&inst->qpu) ||
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v3d_qpu_uses_tlb(&inst->qpu))) {
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c->cursor = vir_before_inst(inst);
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vir_emit_thrsw(c);
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last_thrsw = c->last_thrsw;
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last_thrsw->is_last_thrsw = true;
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}
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}
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}
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/* Make sure c->last_thrsw is the actual last thrsw, not just one we
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* inserted in our most recent unspill.
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*/
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if (last_thrsw)
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c->last_thrsw = last_thrsw;
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c->last_thrsw = last_thrsw;
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/* Don't allow spilling of our spilling instructions. There's no way
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* they can help get things colored.
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