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intel/brw/xe2: Allow int64 conversions

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As far as I can tell from looking at the Bspec, MOV between integers
of all sizes appears to be supported.

shader-db:

total instructions in shared programs: 17480631 -> 17480535 (<.01%)
instructions in affected programs: 26284 -> 26188 (-0.37%)
helped: 21 / HURT: 13

total cycles in shared programs: 897601907 -> 897664293 (<.01%)
cycles in affected programs: 10929664 -> 10992050 (0.57%)
helped: 48 / HURT: 45

fossil-db:

Totals:
Instrs: 140686824 -> 140686155 (-0.00%); split: -0.00%, +0.00%
Cycle count: 21525129188 -> 21524717729 (-0.00%); split: -0.01%, +0.00%
Spill count: 70778 -> 70776 (-0.00%)
Fill count: 139172 -> 139168 (-0.00%)
Max live registers: 47513859 -> 47513795 (-0.00%)

Totals from 612 (0.11% of 549272) affected shaders:
Instrs: 964441 -> 963772 (-0.07%); split: -0.09%, +0.02%
Cycle count: 1215564312 -> 1215152853 (-0.03%); split: -0.09%, +0.06%
Spill count: 16172 -> 16170 (-0.01%)
Fill count: 37962 -> 37958 (-0.01%)
Max live registers: 70749 -> 70685 (-0.09%)

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30700>
This commit is contained in:
Ian Romanick
2024-08-09 15:15:49 -07:00
committed by Marge Bot
parent 09cf9fe8ab
commit c96ceb50d0
1 changed files with 1 additions and 1 deletions
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2
src/intel/compiler/brw_compiler.c
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@@ -146,7 +146,7 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
int64_options |= (nir_lower_icmp64 | nir_lower_minmax64 |
nir_lower_logic64 | nir_lower_ufind_msb64 |
nir_lower_bit_count64 |
nir_lower_bcsel64 | nir_lower_conv64 |
nir_lower_bcsel64 |
nir_lower_extract64 | nir_lower_scan_reduce_bitwise64 |
nir_lower_scan_reduce_iadd64 | nir_lower_subgroup_shuffle64 |
nir_lower_iadd_sat64 | nir_lower_uadd_sat64);