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fd/a7xx: Initialize magic register 8C34 to 0

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This register is set by prop sometimes, functionality is unknown
at the moment.

Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29453>
This commit is contained in:
Mark Collins
2024-03-28 19:52:24 +00:00
committed by Marge Bot
parent 0068e75fc6
commit c85cd9c0b0
2 changed files with 6 additions and 1 deletions
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2
src/freedreno/common/freedreno_devices.py
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@@ -1010,6 +1010,7 @@ add_gpus([
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_88F5, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8C34, 0x00000000],
# Shading rate group
[A6XXRegs.REG_A6XX_RB_UNKNOWN_88F4, 0x00000000],
@@ -1167,6 +1168,7 @@ add_gpus([
[A6XXRegs.REG_A7XX_HLSQ_UNKNOWN_A9AC, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_88F5, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8C34, 0x00000000],
# Shading rate group
[A6XXRegs.REG_A6XX_RB_UNKNOWN_88F4, 0x00000000],

5
src/freedreno/registers/adreno/a6xx.xml
View File

@@ -4476,7 +4476,10 @@ to upconvert to 32b float internally?
<reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1" usage="rp_blit"/>
<reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2" usage="rp_blit"/>
<reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3" usage="rp_blit"/>
<!-- 0x8c34-0x8dff invalid -->
<reg32 offset="0x8c34" name="RB_UNKNOWN_8C34" variants="A7XX-" usage="cmd"/>
<!-- 0x8c35-0x8dff invalid -->
<!-- always 0x1 ? either doesn't exist for a650 or write-only: -->
<reg32 offset="0x8e01" name="RB_UNKNOWN_8E01" usage="cmd"/>