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intel/fs: Always use integer types for indirect MOVs

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There's a new Gen12.5 restriction which forbids using the VxH or Vx1 on
the floating-point pipe.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
This commit is contained in:
Jason Ekstrand
2020-10-29 09:34:08 -05:00
committed by Marge Bot
parent c6a7f4b34e
commit c80c0ed943
3 changed files with 37 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
src/intel/compiler/brw_eu_emit.c
View File

@@ -3473,7 +3473,18 @@ brw_broadcast(struct brw_codegen *p,
assert(src.file == BRW_GENERAL_REGISTER_FILE &&
src.address_mode == BRW_ADDRESS_DIRECT);
assert(!src.abs && !src.negate);
/* Gen12.5 adds the following region restriction:
*
* "Vx1 and VxH indirect addressing for Float, Half-Float, Double-Float
* and Quad-Word data must not be used."
*
* We require the source and destination types to match so stomp to an
* unsigned integer type.
*/
assert(src.type == dst.type);
src.type = dst.type = brw_reg_type_from_bit_size(type_sz(src.type) * 8,
BRW_REGISTER_TYPE_UD);
if ((src.vstride == 0 && (src.hstride == 0 || !align1)) ||
idx.file == BRW_IMMEDIATE_VALUE) {

23
src/intel/compiler/brw_fs_generator.cpp
View File

@@ -462,7 +462,18 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
assert(indirect_byte_offset.type == BRW_REGISTER_TYPE_UD);
assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE);
assert(!reg.abs && !reg.negate);
/* Gen12.5 adds the following region restriction:
*
* "Vx1 and VxH indirect addressing for Float, Half-Float, Double-Float
* and Quad-Word data must not be used."
*
* We require the source and destination types to match so stomp to an
* unsigned integer type.
*/
assert(reg.type == dst.type);
reg.type = dst.type = brw_reg_type_from_bit_size(type_sz(reg.type) * 8,
BRW_REGISTER_TYPE_UD);
unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
@@ -611,6 +622,18 @@ fs_generator::generate_shuffle(fs_inst *inst,
assert((devinfo->verx10 >= 75 && devinfo->has_64bit_float) ||
type_sz(src.type) <= 4);
/* Gen12.5 adds the following region restriction:
*
* "Vx1 and VxH indirect addressing for Float, Half-Float, Double-Float
* and Quad-Word data must not be used."
*
* We require the source and destination types to match so stomp to an
* unsigned integer type.
*/
assert(src.type == dst.type);
src.type = dst.type = brw_reg_type_from_bit_size(type_sz(src.type) * 8,
BRW_REGISTER_TYPE_UD);
/* Because we're using the address register, we're limited to 8-wide
* execution on gfx7. On gfx8, we're limited to 16-wide by the address
* register file and 8-wide for 64-bit types. We could try and make this

5
src/intel/compiler/brw_fs_scoreboard.cpp
View File

@@ -116,8 +116,9 @@ namespace {
return TGL_PIPE_NONE;
else if (devinfo->verx10 < 125)
return TGL_PIPE_FLOAT;
else if (inst->opcode == SHADER_OPCODE_MOV_INDIRECT &&
type_sz(t) >= 8)
else if (inst->opcode == SHADER_OPCODE_MOV_INDIRECT ||
inst->opcode == SHADER_OPCODE_BROADCAST ||
inst->opcode == SHADER_OPCODE_SHUFFLE)
return TGL_PIPE_INT;
else if (inst->opcode == SHADER_OPCODE_BROADCAST &&
!devinfo->has_64bit_float && type_sz(t) >= 8)