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radv: Merge vs state computation with PM4 generation.

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Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
This commit is contained in:
Bas Nieuwenhuizen
2018-01-14 02:43:08 +01:00
parent c4191cf944
commit c80747b32c
2 changed files with 34 additions and 58 deletions
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84
src/amd/vulkan/radv_pipeline.c
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@@ -1606,46 +1606,6 @@ static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
}
}
static void calculate_vs_outinfo(struct radv_pipeline *pipeline)
{
const struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
unsigned clip_dist_mask, cull_dist_mask, total_mask;
clip_dist_mask = outinfo->clip_dist_mask;
cull_dist_mask = outinfo->cull_dist_mask;
total_mask = clip_dist_mask | cull_dist_mask;
bool misc_vec_ena = outinfo->writes_pointsize ||
outinfo->writes_layer ||
outinfo->writes_viewport_index;
pipeline->graphics.vs.pa_cl_vs_out_cntl =
S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
cull_dist_mask << 8 |
clip_dist_mask;
pipeline->graphics.vs.spi_shader_pos_format =
S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
V_02870C_SPI_SHADER_4COMP :
V_02870C_SPI_SHADER_NONE) |
S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
V_02870C_SPI_SHADER_4COMP :
V_02870C_SPI_SHADER_NONE) |
S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
V_02870C_SPI_SHADER_4COMP :
V_02870C_SPI_SHADER_NONE);
pipeline->graphics.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1);
/* only emitted on pre-VI */
pipeline->graphics.vs.vgt_reuse_off = S_028AB4_REUSE_OFF(outinfo->writes_viewport_index);
}
static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
{
uint32_t ps_input_cntl;
@@ -2557,31 +2517,56 @@ radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
{
uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
radeon_set_context_reg(cs, R_0286C4_SPI_VS_OUT_CONFIG,
pipeline->graphics.vs.spi_vs_out_config);
radeon_set_context_reg(cs, R_02870C_SPI_SHADER_POS_FORMAT,
pipeline->graphics.vs.spi_shader_pos_format);
radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
radeon_emit(cs, va >> 8);
radeon_emit(cs, va >> 40);
radeon_emit(cs, shader->rsrc1);
radeon_emit(cs, shader->rsrc2);
const struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
unsigned clip_dist_mask, cull_dist_mask, total_mask;
clip_dist_mask = outinfo->clip_dist_mask;
cull_dist_mask = outinfo->cull_dist_mask;
total_mask = clip_dist_mask | cull_dist_mask;
bool misc_vec_ena = outinfo->writes_pointsize ||
outinfo->writes_layer ||
outinfo->writes_viewport_index;
radeon_set_context_reg(cs, R_0286C4_SPI_VS_OUT_CONFIG,
S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
radeon_set_context_reg(cs, R_02870C_SPI_SHADER_POS_FORMAT,
S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
V_02870C_SPI_SHADER_4COMP :
V_02870C_SPI_SHADER_NONE) |
S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
V_02870C_SPI_SHADER_4COMP :
V_02870C_SPI_SHADER_NONE) |
S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
V_02870C_SPI_SHADER_4COMP :
V_02870C_SPI_SHADER_NONE));
radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
S_028818_VTX_W0_FMT(1) |
S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
pipeline->graphics.vs.pa_cl_vs_out_cntl);
S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
cull_dist_mask << 8 |
clip_dist_mask);
if (pipeline->device->physical_device->rad_info.chip_class <= VI)
radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
pipeline->graphics.vs.vgt_reuse_off);
outinfo->writes_viewport_index);
}
static void
@@ -3019,7 +3004,6 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
pipeline->graphics.shader_z_format = shader_z_format;
calculate_vgt_gs_mode(pipeline);
calculate_vs_outinfo(pipeline);
calculate_ps_inputs(pipeline);
for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {