gallium: add cap to export device pointer size

v2: document the new cap
v3: fix 80 char limit in screen.rst

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

src/gallium/docs/source/screen.rst

@@ -496,6 +496,8 @@ pipe_screen::get_compute_param.
   non-zero means yes, zero means no. Value type: ``uint32_t``
 * ``PIPE_COMPUTE_CAP_SUBGROUP_SIZE``: The size of a basic execution unit in
   threads. Also known as wavefront size, warp size or SIMD width.
+* ``PIPE_COMPUTE_CAP_ADDRESS_BITS``: The default compute device address space
+  size specified as an unsigned integer value in bits.
 
 .. _pipe_bind:
 

src/gallium/drivers/ilo/ilo_screen.c

@@ -199,6 +199,7 @@ ilo_get_compute_param(struct pipe_screen *screen,
       uint32_t max_compute_units;
       uint32_t images_supported;
       uint32_t subgroup_size;
+      uint32_t address_bits;
    } val;
    const void *ptr;
    int size;
@@ -266,6 +267,11 @@ ilo_get_compute_param(struct pipe_screen *screen,
       ptr = &val.max_input_size;
       size = sizeof(val.max_input_size);
       break;
+   case PIPE_COMPUTE_CAP_ADDRESS_BITS:
+      val.address_bits = 32;
+      ptr = &val.address_bits;
+      size = sizeof(val.address_bits);
+      break;
    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
       val.max_mem_alloc_size = 1u << 31;
 

src/gallium/drivers/nouveau/nv50/nv50_screen.c

@@ -418,6 +418,8 @@ nv50_screen_get_compute_param(struct pipe_screen *pscreen,
       RET((uint32_t []) { screen->mp_count });
    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
+   case PIPE_COMPUTE_CAP_ADDRESS_BITS:
+      RET((uint32_t []) { 32 });
    default:
       return 0;
    }

src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

@@ -479,6 +479,8 @@ nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
       RET((uint32_t []) { screen->mp_count_compute });
    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
+   case PIPE_COMPUTE_CAP_ADDRESS_BITS:
+      RET((uint32_t []) { 64 });
    default:
       return 0;
    }

src/gallium/drivers/radeon/r600_pipe_common.c

@@ -881,6 +881,14 @@ static int r600_get_compute_param(struct pipe_screen *screen,
 				*max_threads_per_block = 256;
 		}
 		return sizeof(uint64_t);
+	case PIPE_COMPUTE_CAP_ADDRESS_BITS:
+		if (ret) {
+			uint32_t *address_bits = ret;
+			address_bits[0] = 32;
+			if (rscreen->chip_class >= SI)
+				address_bits[0] = 64;
+		}
+		return 1 * sizeof(uint32_t);
 
 	case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 		if (ret) {

src/gallium/drivers/softpipe/sp_screen.c

@@ -521,6 +521,7 @@ softpipe_get_compute_param(struct pipe_screen *_screen,
    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
+   case PIPE_COMPUTE_CAP_ADDRESS_BITS:
       break;
    }
    return 0;

src/gallium/include/pipe/p_defines.h

@@ -834,6 +834,7 @@ enum pipe_shader_ir
  */
 enum pipe_compute_cap
 {
+   PIPE_COMPUTE_CAP_ADDRESS_BITS,
    PIPE_COMPUTE_CAP_IR_TARGET,
    PIPE_COMPUTE_CAP_GRID_DIMENSION,
    PIPE_COMPUTE_CAP_MAX_GRID_SIZE,