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radv: remove radv_graphics_pipeline::can_use_simple_input

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Use the VS shader info instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22192>
This commit is contained in:
Samuel Pitoiset
2023-03-29 16:12:09 +02:00
committed by Marge Bot
parent 53b2b30d0b
commit c7784f1409
3 changed files with 8 additions and 11 deletions
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11
src/amd/vulkan/radv_cmd_buffer.c
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@@ -3657,7 +3657,6 @@ lookup_vs_prolog(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *v
assert(vs_shader->info.vs.dynamic_inputs); assert(vs_shader->info.vs.dynamic_inputs);
const struct radv_vs_input_state *state = &cmd_buffer->state.dynamic_vs_input; const struct radv_vs_input_state *state = &cmd_buffer->state.dynamic_vs_input;
struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
struct radv_device *device = cmd_buffer->device; struct radv_device *device = cmd_buffer->device;
unsigned num_attributes = util_last_bit(vs_shader->info.vs.vb_desc_usage_mask); unsigned num_attributes = util_last_bit(vs_shader->info.vs.vb_desc_usage_mask);
@@ -3686,10 +3685,16 @@ lookup_vs_prolog(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *v
} }
misaligned_mask |= state->nontrivial_formats; misaligned_mask |= state->nontrivial_formats;
const bool can_use_simple_input =
cmd_buffer->state.shaders[MESA_SHADER_VERTEX] &&
cmd_buffer->state.shaders[MESA_SHADER_VERTEX]->info.is_ngg ==
device->physical_device->use_ngg &&
cmd_buffer->state.shaders[MESA_SHADER_VERTEX]->info.wave_size ==
device->physical_device->ge_wave_size;
/* try to use a pre-compiled prolog first */ /* try to use a pre-compiled prolog first */
struct radv_shader_part *prolog = NULL; struct radv_shader_part *prolog = NULL;
if (pipeline->can_use_simple_input && if (can_use_simple_input && (!vs_shader->info.vs.as_ls || !instance_rate_inputs) &&
(!vs_shader->info.vs.as_ls || !instance_rate_inputs) &&
!misaligned_mask && !state->alpha_adjust_lo && !state->alpha_adjust_hi) { !misaligned_mask && !state->alpha_adjust_lo && !state->alpha_adjust_hi) {
if (!instance_rate_inputs) { if (!instance_rate_inputs) {
prolog = device->simple_vs_prologs[num_attributes - 1]; prolog = device->simple_vs_prologs[num_attributes - 1];

7
src/amd/vulkan/radv_pipeline.c
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@@ -4409,13 +4409,6 @@ radv_pipeline_init_vertex_input_state(const struct radv_device *device,
} }
} }
if (pipeline->base.shaders[MESA_SHADER_VERTEX]) {
const struct radv_shader *vs_shader = pipeline->base.shaders[MESA_SHADER_VERTEX];
pipeline->can_use_simple_input = vs_shader->info.is_ngg == pdevice->use_ngg &&
vs_shader->info.wave_size == pdevice->ge_wave_size;
} else {
pipeline->can_use_simple_input = false;
}
if (vs_info->vs.dynamic_inputs) if (vs_info->vs.dynamic_inputs)
pipeline->vb_desc_usage_mask = BITFIELD_MASK(util_last_bit(vs_info->vs.vb_desc_usage_mask)); pipeline->vb_desc_usage_mask = BITFIELD_MASK(util_last_bit(vs_info->vs.vb_desc_usage_mask));
else else

1
src/amd/vulkan/radv_private.h
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@@ -2203,7 +2203,6 @@ struct radv_graphics_pipeline {
bool uses_drawid; bool uses_drawid;
bool uses_baseinstance; bool uses_baseinstance;
bool can_use_simple_input;
/* Whether the pipeline uses inner coverage which means that a fragment has all of its pixel /* Whether the pipeline uses inner coverage which means that a fragment has all of its pixel
* squares fully covered by the generating primitive. * squares fully covered by the generating primitive.