diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index c7d10436059..2a8507c8c97 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3657,7 +3657,6 @@ lookup_vs_prolog(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *v
    assert(vs_shader->info.vs.dynamic_inputs);
 
    const struct radv_vs_input_state *state = &cmd_buffer->state.dynamic_vs_input;
-   struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
    struct radv_device *device = cmd_buffer->device;
 
    unsigned num_attributes = util_last_bit(vs_shader->info.vs.vb_desc_usage_mask);
@@ -3686,10 +3685,16 @@ lookup_vs_prolog(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *v
    }
    misaligned_mask |= state->nontrivial_formats;
 
+   const bool can_use_simple_input =
+      cmd_buffer->state.shaders[MESA_SHADER_VERTEX] &&
+      cmd_buffer->state.shaders[MESA_SHADER_VERTEX]->info.is_ngg ==
+         device->physical_device->use_ngg &&
+      cmd_buffer->state.shaders[MESA_SHADER_VERTEX]->info.wave_size ==
+         device->physical_device->ge_wave_size;
+
    /* try to use a pre-compiled prolog first */
    struct radv_shader_part *prolog = NULL;
-   if (pipeline->can_use_simple_input &&
-       (!vs_shader->info.vs.as_ls || !instance_rate_inputs) &&
+   if (can_use_simple_input && (!vs_shader->info.vs.as_ls || !instance_rate_inputs) &&
        !misaligned_mask && !state->alpha_adjust_lo && !state->alpha_adjust_hi) {
       if (!instance_rate_inputs) {
          prolog = device->simple_vs_prologs[num_attributes - 1];
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 55c7c814669..186712134c0 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -4409,13 +4409,6 @@ radv_pipeline_init_vertex_input_state(const struct radv_device *device,
       }
    }
 
-   if (pipeline->base.shaders[MESA_SHADER_VERTEX]) {
-      const struct radv_shader *vs_shader = pipeline->base.shaders[MESA_SHADER_VERTEX];
-      pipeline->can_use_simple_input = vs_shader->info.is_ngg == pdevice->use_ngg &&
-                                       vs_shader->info.wave_size == pdevice->ge_wave_size;
-   } else {
-      pipeline->can_use_simple_input = false;
-   }
    if (vs_info->vs.dynamic_inputs)
       pipeline->vb_desc_usage_mask = BITFIELD_MASK(util_last_bit(vs_info->vs.vb_desc_usage_mask));
    else
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 97540bf52ed..088db6b430e 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -2203,7 +2203,6 @@ struct radv_graphics_pipeline {
 
    bool uses_drawid;
    bool uses_baseinstance;
-   bool can_use_simple_input;
 
    /* Whether the pipeline uses inner coverage which means that a fragment has all of its pixel
     * squares fully covered by the generating primitive.