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anv: Add and use emit_pipeline_select()

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To avoid the replication of code to properly emit PIPELINE_SELECT.

init_compute_queue_state() had a different emit of PIPELINE_SELECT but
as there is no compute engine in GFX VER 11 we are safe with the
differences.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20444>
This commit is contained in:
José Roberto de Souza
2022-12-26 09:34:23 -08:00
parent 57f73d097e
commit c6d1f76da2
4 changed files with 18 additions and 24 deletions
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1
src/intel/vulkan/anv_genX.h
View File

@@ -81,6 +81,7 @@ void genX(cmd_buffer_emit_hashing_mode)(struct anv_cmd_buffer *cmd_buffer,
void genX(flush_pipeline_select_3d)(struct anv_cmd_buffer *cmd_buffer);
void genX(flush_pipeline_select_gpgpu)(struct anv_cmd_buffer *cmd_buffer);
void genX(emit_pipeline_select)(struct anv_batch *batch, uint32_t pipeline);
enum anv_pipe_bits
genX(emit_apply_pipe_flushes)(struct anv_batch *batch,

19
src/intel/vulkan/genX_cmd_buffer.c
View File

@@ -6274,6 +6274,19 @@ genX(CmdTraceRaysIndirect2KHR)(
#endif /* GFX_VERx10 >= 125 */
/* Only emit PIPELINE_SELECT, for the whole mode switch and flushing use
* flush_pipeline_select()
*/
void
genX(emit_pipeline_select)(struct anv_batch *batch, uint32_t pipeline)
{
anv_batch_emit(batch, GENX(PIPELINE_SELECT), ps) {
ps.MaskBits = GFX_VER >= 12 ? 0x13 : 3;
ps.MediaSamplerDOPClockGateEnable = GFX_VER >= 12;
ps.PipelineSelection = pipeline;
}
}
static void
genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
uint32_t pipeline)
@@ -6345,11 +6358,7 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
"flush and invalidate for PIPELINE_SELECT");
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) {
ps.MaskBits = GFX_VER >= 12 ? 0x13 : 3;
ps.MediaSamplerDOPClockGateEnable = GFX_VER >= 12;
ps.PipelineSelection = pipeline;
}
genX(emit_pipeline_select)(&cmd_buffer->batch, pipeline);
#if GFX_VER == 9
if (devinfo->platform == INTEL_PLATFORM_GLK) {

7
src/intel/vulkan/genX_gpu_memcpy.c
View File

@@ -243,12 +243,7 @@ genX(emit_so_memcpy_init)(struct anv_memcpy_state *state,
const struct intel_l3_config *cfg = intel_get_default_l3_config(device->info);
genX(emit_l3_config)(batch, device, cfg);
anv_batch_emit(batch, GENX(PIPELINE_SELECT), ps) {
ps.MaskBits = GFX_VER >= 12 ? 0x13 : 3;
ps.MediaSamplerDOPClockGateEnable = GFX_VER >= 12;
ps.PipelineSelection = _3D;
}
genX(emit_pipeline_select)(batch, _3D);
emit_common_so_memcpy(batch, device, cfg);
}

15
src/intel/vulkan/genX_state.c
View File

@@ -274,11 +274,7 @@ init_render_queue_state(struct anv_queue *queue)
.end = (void *) cmds + sizeof(cmds),
};
anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {
ps.MaskBits = GFX_VER >= 12 ? 0x13 : 3;
ps.MediaSamplerDOPClockGateEnable = GFX_VER >= 12;
ps.PipelineSelection = _3D;
}
genX(emit_pipeline_select)(&batch, _3D);
#if GFX_VER == 9
anv_batch_write_reg(&batch, GENX(CACHE_MODE_1), cm1) {
@@ -490,14 +486,7 @@ init_compute_queue_state(struct anv_queue *queue)
batch.start = batch.next = cmds;
batch.end = (void *) cmds + sizeof(cmds);
anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {
ps.MaskBits = 3;
#if GFX_VER >= 11
ps.MaskBits |= 0x10;
ps.MediaSamplerDOPClockGateEnable = true;
#endif
ps.PipelineSelection = GPGPU;
}
genX(emit_pipeline_select)(&batch, GPGPU);
init_common_queue_state(queue, &batch);