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radv/winsys: add a ring level detection for ib bo usage.

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The video rings can't use IB bos

v2: add use_ib flag to avoid a bunch of checks.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15257>
This commit is contained in:
Dave Airlie
2022-03-07 10:45:03 +10:00
parent 31b82afe6e
commit c6755e85e3
1 changed files with 25 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

34
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
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@@ -69,6 +69,7 @@ struct radv_amdgpu_cs {
unsigned *ib_size_ptr;
VkResult status;
bool is_chained;
bool use_ib;
int buffer_hash_table[1024];
unsigned hw_ip;
@@ -106,6 +107,19 @@ radv_amdgpu_cs(struct radeon_cmdbuf *base)
return (struct radv_amdgpu_cs *)base;
}
static bool
ring_can_use_ib_bos(const struct radv_amdgpu_winsys *ws,
enum ring_type ring_type)
{
if (ring_type == RING_UVD ||
ring_type == RING_VCE ||
ring_type == RING_UVD_ENC ||
ring_type == RING_VCN_DEC ||
ring_type == RING_VCN_ENC)
return false;
return ws->use_ib_bos;
}
static int
ring_to_hw_ip(enum ring_type ring)
{
@@ -268,7 +282,9 @@ radv_amdgpu_cs_create(struct radeon_winsys *ws, enum ring_type ring_type)
cs->ws = radv_amdgpu_winsys(ws);
radv_amdgpu_init_cs(cs, ring_type);
if (cs->ws->use_ib_bos) {
cs->use_ib = ring_can_use_ib_bos(cs->ws, ring_type);
if (cs->use_ib) {
VkResult result =
ws->buffer_create(ws, ib_size, 0, radv_amdgpu_cs_domain(ws),
RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING |
@@ -339,7 +355,7 @@ radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, size_t min_size)
return;
}
if (!cs->ws->use_ib_bos) {
if (!cs->use_ib) {
const uint64_t limit_dws = GFX6_MAX_CS_SIZE;
uint64_t ib_dws = MAX2(cs->base.cdw + min_size, MIN2(cs->base.max_dw * 2, limit_dws));
@@ -458,9 +474,9 @@ static VkResult
radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs)
{
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
enum ring_type ring_type = hw_ip_to_ring(cs->hw_ip);
if (cs->ws->use_ib_bos) {
enum ring_type ring_type = hw_ip_to_ring(cs->hw_ip);
if (cs->use_ib) {
uint32_t ib_pad_dw_mask = MAX2(3, cs->ws->info.ib_pad_dw_mask[ring_type]);
uint32_t nop_packet = get_nop_packet(cs);
@@ -510,7 +526,7 @@ radv_amdgpu_cs_reset(struct radeon_cmdbuf *_cs)
cs->num_buffers = 0;
cs->num_virtual_buffers = 0;
if (cs->ws->use_ib_bos) {
if (cs->use_ib) {
cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer);
for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i)
@@ -658,7 +674,7 @@ radv_amdgpu_cs_execute_secondary(struct radeon_cmdbuf *_parent, struct radeon_cm
struct radv_amdgpu_cs *parent = radv_amdgpu_cs(_parent);
struct radv_amdgpu_cs *child = radv_amdgpu_cs(_child);
struct radv_amdgpu_winsys *ws = parent->ws;
bool use_ib2 = ws->use_ib_bos && allow_ib2;
bool use_ib2 = parent->use_ib && allow_ib2;
if (parent->status != VK_SUCCESS || child->status != VK_SUCCESS)
return;
@@ -682,7 +698,7 @@ radv_amdgpu_cs_execute_secondary(struct radeon_cmdbuf *_parent, struct radeon_cm
radeon_emit(&parent->base, child->ib.ib_mc_address >> 32);
radeon_emit(&parent->base, child->ib.size);
} else {
if (parent->ws->use_ib_bos) {
if (parent->use_ib) {
/* Copy and chain old IB buffers from the child to the parent IB. */
for (unsigned i = 0; i < child->num_old_ib_buffers; i++) {
struct radv_amdgpu_ib *ib = &child->old_ib_buffers[i];
@@ -1364,7 +1380,7 @@ radv_amdgpu_winsys_cs_submit_internal(struct radeon_winsys_ctx *_ctx, enum ring_
assert(sem_info);
if (!cs_count) {
result = radv_amdgpu_cs_submit_zero(ctx, ring_type, queue_idx, sem_info);
} else if (!ctx->ws->use_ib_bos) {
} else if (!ring_can_use_ib_bos(ctx->ws, ring_type)) {
result = radv_amdgpu_winsys_cs_submit_sysmem(_ctx, queue_idx, sem_info, cs_array, cs_count,
initial_preamble_cs, continue_preamble_cs);
} else if (can_patch) {
@@ -1492,7 +1508,7 @@ radv_amdgpu_winsys_cs_dump(struct radeon_cmdbuf *_cs, FILE *file, const int *tra
void *ib = cs->base.buf;
int num_dw = cs->base.cdw;
if (cs->ws->use_ib_bos) {
if (cs->use_ib) {
ib = radv_amdgpu_winsys_get_cpu_addr(cs, cs->ib.ib_mc_address);
num_dw = cs->ib.size;
}