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radv: Fix sample locations at 0 for X/Y

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We cannot set the {X,Y}MAX_RIGHT_EXCLUSION bits
if we have a sample location at a pixel boundary.

CTS does not seem to be catching this.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Co-authored-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31839>
This commit is contained in:
Joshua Ashton
2024-03-18 11:00:08 +00:00
committed by Marge Bot
parent 130a423118
commit c66fd95d92
3 changed files with 26 additions and 6 deletions
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17
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -1240,6 +1240,23 @@ radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
} }
radeon_emit(cs, centroid_priority); radeon_emit(cs, centroid_priority);
radeon_emit(cs, centroid_priority >> 32); radeon_emit(cs, centroid_priority >> 32);
if (pdev->info.gfx_level >= GFX7) {
/* The exclusion bits can be set to improve rasterization efficiency if no sample lies on the pixel boundary
* (-8 sample offset).
*/
uint32_t pa_su_prim_filter_cntl = S_02882C_XMAX_RIGHT_EXCLUSION(1) | S_02882C_YMAX_BOTTOM_EXCLUSION(1);
for (uint32_t i = 0; i < 4; ++i) {
for (uint32_t j = 0; j < num_samples; ++j) {
if (sample_locs[i][j].x <= -8)
pa_su_prim_filter_cntl &= C_02882C_XMAX_RIGHT_EXCLUSION;
if (sample_locs[i][j].y <= -8)
pa_su_prim_filter_cntl &= C_02882C_YMAX_BOTTOM_EXCLUSION;
}
}
radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, pa_su_prim_filter_cntl);
}
} }
static void static void

9
src/amd/vulkan/radv_device.c
View File

@@ -995,6 +995,15 @@ radv_emit_default_sample_locations(const struct radv_physical_device *pdev, stru
break; break;
} }
/* The exclusion bits can be set to improve rasterization efficiency if no sample lies on the
* pixel boundary (-8 sample offset). It's currently always TRUE because the driver doesn't
* support 16 samples.
*/
if (pdev->info.gfx_level >= GFX7) {
radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
S_02882C_XMAX_RIGHT_EXCLUSION(1) | S_02882C_YMAX_BOTTOM_EXCLUSION(1));
}
if (pdev->info.gfx_level >= GFX12) { if (pdev->info.gfx_level >= GFX12) {
radeon_set_context_reg_seq(cs, R_028BF0_PA_SC_CENTROID_PRIORITY_0, 2); radeon_set_context_reg_seq(cs, R_028BF0_PA_SC_CENTROID_PRIORITY_0, 2);
} else { } else {

6
src/amd/vulkan/radv_queue.c
View File

@@ -770,12 +770,6 @@ radv_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0); radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
} }
if (pdev->info.gfx_level >= GFX7) {
/* If any sample location uses the -8 coordinate, the EXCLUSION fields should be set to 0. */
radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
S_02882C_XMAX_RIGHT_EXCLUSION(1) | S_02882C_YMAX_BOTTOM_EXCLUSION(1));
}
if (pdev->info.gfx_level <= GFX8) if (pdev->info.gfx_level <= GFX8)
radeon_set_sh_reg(cs, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(pdev->info.address32_hi >> 8)); radeon_set_sh_reg(cs, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(pdev->info.address32_hi >> 8));