panfrost: Preprocess shaders at CSO create time
Now the only passes that depend on the shader key can run late, so we can preprocess ahead-of-time once and throw away the original shader. This reduces the cost of shader variants, as well as deduplicates some lowering for transform feedback shaders. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
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@@ -339,6 +339,9 @@ struct panfrost_uncompiled_shader {
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* shaders for desktop GL.
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*/
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uint32_t fixed_varying_mask;
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/* If gl_FragColor was lowered, we need to optimize the stores later */
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bool fragcolor_lowered;
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};
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/* The binary artefacts of compiling a shader. This differs from
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@@ -95,19 +95,21 @@ panfrost_shader_compile(struct panfrost_screen *screen, const nir_shader *ir,
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/* Lower this early so the backends don't have to worry about it */
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if (s->info.stage == MESA_SHADER_FRAGMENT) {
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inputs.fixed_varying_mask = key->fs.fixed_varying_mask;
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if (s->info.outputs_written & BITFIELD_BIT(FRAG_RESULT_COLOR)) {
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NIR_PASS_V(s, nir_lower_fragcolor, 8);
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}
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} else if (s->info.stage == MESA_SHADER_VERTEX) {
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inputs.fixed_varying_mask = fixed_varying_mask;
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/* No IDVS for internal XFB shaders */
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inputs.no_idvs = s->info.has_transform_feedback_varyings;
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if (s->info.has_transform_feedback_varyings) {
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NIR_PASS_V(s, nir_io_add_const_offset_to_base,
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nir_var_shader_in | nir_var_shader_out);
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NIR_PASS_V(s, nir_io_add_intrinsic_xfb_info);
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NIR_PASS_V(s, pan_lower_xfb);
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}
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}
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util_dynarray_init(&out->binary, NULL);
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pan_shader_preprocess(s, inputs.gpu_id);
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if (s->info.stage == MESA_SHADER_FRAGMENT) {
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if (key->fs.nr_cbufs_for_fragcolor) {
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@@ -194,8 +196,11 @@ panfrost_shader_get(struct pipe_screen *pscreen,
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static void
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panfrost_build_key(struct panfrost_context *ctx,
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struct panfrost_shader_key *key, const nir_shader *nir)
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struct panfrost_shader_key *key,
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struct panfrost_uncompiled_shader *uncompiled)
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{
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const nir_shader *nir = uncompiled->nir;
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/* We don't currently have vertex shader variants */
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if (nir->info.stage != MESA_SHADER_FRAGMENT)
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return;
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@@ -206,7 +211,7 @@ panfrost_build_key(struct panfrost_context *ctx,
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struct panfrost_uncompiled_shader *vs = ctx->uncompiled[MESA_SHADER_VERTEX];
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/* gl_FragColor lowering needs the number of colour buffers */
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if (nir->info.outputs_written & BITFIELD_BIT(FRAG_RESULT_COLOR)) {
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if (uncompiled->fragcolor_lowered) {
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key->fs.nr_cbufs_for_fragcolor = fb->nr_cbufs;
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}
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@@ -299,7 +304,7 @@ panfrost_update_shader_variant(struct panfrost_context *ctx,
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simple_mtx_lock(&uncompiled->lock);
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struct panfrost_shader_key key = {0};
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panfrost_build_key(ctx, &key, uncompiled->nir);
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panfrost_build_key(ctx, &key, uncompiled);
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util_dynarray_foreach(&uncompiled->variants, struct panfrost_compiled_shader,
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so) {
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@@ -361,6 +366,18 @@ panfrost_create_shader_state(struct pipe_context *pctx,
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~VARYING_BIT_POS & ~VARYING_BIT_PSIZ;
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}
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/* gl_FragColor needs to be lowered before lowering I/O, do that now */
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if (nir->info.stage == MESA_SHADER_FRAGMENT &&
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nir->info.outputs_written & BITFIELD_BIT(FRAG_RESULT_COLOR)) {
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NIR_PASS_V(nir, nir_lower_fragcolor, 8);
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so->fragcolor_lowered = true;
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}
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/* Then run the suite of lowering and optimization, including I/O lowering */
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struct panfrost_device *dev = pan_device(pctx->screen);
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pan_shader_preprocess(nir, dev->gpu_id);
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/* If this shader uses transform feedback, compile the transform
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* feedback program. This is a special shader variant.
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*/
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@@ -397,11 +414,8 @@ panfrost_create_shader_state(struct pipe_context *pctx,
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* gl_FragColor is used, there is only a single render target. The
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* implicit broadcast is neither especially useful nor required by GLES.
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*/
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if (so->nir->info.stage == MESA_SHADER_FRAGMENT &&
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so->nir->info.outputs_written & BITFIELD_BIT(FRAG_RESULT_COLOR)) {
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if (so->fragcolor_lowered)
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key.fs.nr_cbufs_for_fragcolor = 1;
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}
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/* Creating a CSO is single-threaded, so it's ok to use the
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* locked function without explicitly taking the lock. Creating a
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@@ -4815,16 +4815,7 @@ bifrost_preprocess_nir(nir_shader *nir, unsigned gpu_id)
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NIR_PASS_V(nir, pan_lower_sample_pos);
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NIR_PASS_V(nir, nir_lower_bit_size, bi_lower_bit_size, NULL);
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NIR_PASS_V(nir, nir_lower_64bit_phis);
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if (nir->xfb_info != NULL && nir->info.has_transform_feedback_varyings) {
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NIR_PASS_V(nir, nir_io_add_const_offset_to_base,
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nir_var_shader_in | nir_var_shader_out);
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NIR_PASS_V(nir, nir_io_add_intrinsic_xfb_info);
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NIR_PASS_V(nir, pan_lower_xfb);
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}
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NIR_PASS_V(nir, nir_lower_regs_to_ssa);
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NIR_PASS_V(nir, pan_nir_lower_64bit_intrin);
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NIR_PASS_V(nir, pan_lower_helper_invocation);
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NIR_PASS_V(nir, nir_lower_int64);
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@@ -402,14 +402,6 @@ midgard_preprocess_nir(nir_shader *nir, unsigned gpu_id)
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NIR_PASS_V(nir, pan_lower_helper_invocation);
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NIR_PASS_V(nir, pan_lower_sample_pos);
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if (nir->xfb_info != NULL && nir->info.has_transform_feedback_varyings) {
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NIR_PASS_V(nir, nir_io_add_const_offset_to_base,
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nir_var_shader_in | nir_var_shader_out);
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NIR_PASS_V(nir, nir_io_add_intrinsic_xfb_info);
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NIR_PASS_V(nir, pan_lower_xfb);
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}
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NIR_PASS_V(nir, midgard_nir_lower_algebraic_early);
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NIR_PASS_V(nir, nir_lower_alu_to_scalar, mdg_should_scalarize, NULL);
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NIR_PASS_V(nir, nir_lower_flrp, 16 | 32 | 64, false /* always_precise */);
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