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ac/nir,radv/llvm: add support for the attribute ring

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19216>
This commit is contained in:
Samuel Pitoiset
2022-10-20 04:40:50 +00:00
parent fee5e379f4
commit c5bf63753d
2 changed files with 12 additions and 0 deletions
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1
src/amd/llvm/ac_nir_to_llvm.c
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@@ -3605,6 +3605,7 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
case nir_intrinsic_load_ring_tess_offchip_offset_amd:
case nir_intrinsic_load_ring_esgs_amd:
case nir_intrinsic_load_ring_es2gs_offset_amd:
case nir_intrinsic_load_ring_attr_amd:
case nir_intrinsic_load_lshs_vertex_stride_amd:
case nir_intrinsic_load_tcs_num_patches_amd:
case nir_intrinsic_load_hs_out_patch_data_offset_amd:

11
src/amd/vulkan/radv_nir_to_llvm.c
View File

@@ -66,6 +66,7 @@ struct radv_shader_context {
LLVMValueRef gsvs_ring[4];
LLVMValueRef hs_ring_tess_offchip;
LLVMValueRef hs_ring_tess_factor;
LLVMValueRef attr_ring;
uint64_t output_mask;
};
@@ -1257,6 +1258,14 @@ ac_setup_rings(struct radv_shader_context *ctx)
ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(
&ctx->ac, ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
}
if (ctx->options->gfx_level >= GFX11 &&
((ctx->stage == MESA_SHADER_VERTEX && !ctx->shader_info->vs.as_es && !ctx->shader_info->vs.as_ls) ||
(ctx->stage == MESA_SHADER_TESS_EVAL && !ctx->shader_info->tes.as_es) ||
(ctx->stage == MESA_SHADER_GEOMETRY))) {
ctx->attr_ring = ac_build_load_to_sgpr(&ctx->ac, ring_offsets,
LLVMConstInt(ctx->ac.i32, RING_PS_ATTR, false));
}
}
/* Fixup the HW not emitting the TCS regs if there are no HS threads. */
@@ -1321,6 +1330,8 @@ static LLVMValueRef radv_intrinsic_load(struct ac_shader_abi *abi, nir_intrinsic
return ctx->hs_ring_tess_offchip;
case nir_intrinsic_load_ring_esgs_amd:
return ctx->esgs_ring;
case nir_intrinsic_load_ring_attr_amd:
return ctx->attr_ring;
default:
return NULL;
}