OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel/fs: fix shader call lowering pass

Browse Source 
Now that we removed the intel intrinsic and just use the generic one,
we can skip it in the intel call lowering pass and just deal with it
in the intel rt intrinsic lowering.

v2: rewrite with nir_shader_instructions_pass() (Jason)

v3: handle everything in switch (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 423c47de99 ("nir: drop the btd_resume_intel intrinsic")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12113>
This commit is contained in:
Lionel Landwerlin
2021-06-29 12:40:39 +03:00
committed by Marge Bot
parent 724a38eb94
commit c5a42e4010
1 changed files with 115 additions and 134 deletions
Download Patch File Download Diff File Expand all files Collapse all files

89
src/intel/compiler/brw_nir_lower_shader_calls.c
View File

@@ -124,29 +124,16 @@ store_resume_addr(nir_builder *b, nir_intrinsic_instr *call)
nir_btd_stack_push_intel(b, offset); nir_btd_stack_push_intel(b, offset);
} }
bool static bool
brw_nir_lower_shader_calls(nir_shader *shader) lower_shader_calls_instr(struct nir_builder *b, nir_instr *instr, void *data)
{ {
nir_function_impl *impl = nir_shader_get_entrypoint(shader);
bool progress = false;
nir_builder _b, *b = &_b;
nir_builder_init(&_b, impl);
nir_foreach_block_safe(block, impl) {
nir_foreach_instr_safe(instr, block) {
if (instr->type != nir_instr_type_intrinsic) if (instr->type != nir_instr_type_intrinsic)
continue; return false;
/* Leave nir_intrinsic_rt_resume to be lowered by
* brw_nir_lower_rt_intrinsics()
*/
nir_intrinsic_instr *call = nir_instr_as_intrinsic(instr); nir_intrinsic_instr *call = nir_instr_as_intrinsic(instr);
if (call->intrinsic != nir_intrinsic_rt_trace_ray &&
call->intrinsic != nir_intrinsic_rt_execute_callable &&
call->intrinsic != nir_intrinsic_rt_resume)
continue;
b->cursor = nir_before_instr(instr);
progress = true;
switch (call->intrinsic) { switch (call->intrinsic) {
case nir_intrinsic_rt_trace_ray: { case nir_intrinsic_rt_trace_ray: {
@@ -156,15 +143,14 @@ brw_nir_lower_shader_calls(nir_shader *shader)
nir_ssa_def *ray_flags = call->src[1].ssa; nir_ssa_def *ray_flags = call->src[1].ssa;
/* From the SPIR-V spec: /* From the SPIR-V spec:
* *
* "Only the 8 least-significant bits of Cull Mask are used by * "Only the 8 least-significant bits of Cull Mask are used by this
* this instruction - other bits are ignored. * instruction - other bits are ignored.
* *
* Only the 4 least-significant bits of SBT Offset and SBT * Only the 4 least-significant bits of SBT Offset and SBT Stride are
* Stride are used by this instruction - other bits are * used by this instruction - other bits are ignored.
* ignored.
* *
* Only the 16 least-significant bits of Miss Index are used by * Only the 16 least-significant bits of Miss Index are used by this
* this instruction - other bits are ignored." * instruction - other bits are ignored."
*/ */
nir_ssa_def *cull_mask = nir_iand_imm(b, call->src[2].ssa, 0xff); nir_ssa_def *cull_mask = nir_iand_imm(b, call->src[2].ssa, 0xff);
nir_ssa_def *sbt_offset = nir_iand_imm(b, call->src[3].ssa, 0xf); nir_ssa_def *sbt_offset = nir_iand_imm(b, call->src[3].ssa, 0xf);
@@ -176,24 +162,24 @@ brw_nir_lower_shader_calls(nir_shader *shader)
nir_ssa_def *ray_t_max = call->src[9].ssa; nir_ssa_def *ray_t_max = call->src[9].ssa;
/* The hardware packet takes the address to the root node in the /* The hardware packet takes the address to the root node in the
* acceleration structure, not the acceleration structure itself. * acceleration structure, not the acceleration structure itself. To
* To find that, we have to read the root node offset from the * find that, we have to read the root node offset from the acceleration
* acceleration structure which is the first QWord. * structure which is the first QWord.
*/ */
nir_ssa_def *root_node_ptr = nir_ssa_def *root_node_ptr =
nir_iadd(b, as_addr, nir_load_global(b, as_addr, 256, 1, 64)); nir_iadd(b, as_addr, nir_load_global(b, as_addr, 256, 1, 64));
/* The hardware packet requires an address to the first element of /* The hardware packet requires an address to the first element of the
* the hit SBT. * hit SBT.
* *
* In order to calculate this, we must multiply the "SBT Offset" * In order to calculate this, we must multiply the "SBT Offset"
* provided to OpTraceRay by the SBT stride provided for the hit * provided to OpTraceRay by the SBT stride provided for the hit SBT in
* SBT in the call to vkCmdTraceRay() and add that to the base * the call to vkCmdTraceRay() and add that to the base address of the
* address of the hit SBT. This stride is not to be confused with * hit SBT. This stride is not to be confused with the "SBT Stride"
* the "SBT Stride" provided to OpTraceRay which is in units of * provided to OpTraceRay which is in units of this stride. It's a
* this stride. It's a rather terrible overload of the word * rather terrible overload of the word "stride". The hardware docs
* "stride". The hardware docs calls the SPIR-V stride value the * calls the SPIR-V stride value the "shader index multiplier" which is
* "shader index multiplier" which is a much more sane name. * a much more sane name.
*/ */
nir_ssa_def *hit_sbt_stride_B = nir_ssa_def *hit_sbt_stride_B =
nir_load_ray_hit_sbt_stride_intel(b); nir_load_ray_hit_sbt_stride_intel(b);
@@ -227,7 +213,7 @@ brw_nir_lower_shader_calls(nir_shader *shader)
}; };
brw_nir_rt_store_mem_ray(b, &ray_defs, BRW_RT_BVH_LEVEL_WORLD); brw_nir_rt_store_mem_ray(b, &ray_defs, BRW_RT_BVH_LEVEL_WORLD);
nir_trace_ray_initial_intel(b); nir_trace_ray_initial_intel(b);
break; return true;
} }
case nir_intrinsic_rt_execute_callable: { case nir_intrinsic_rt_execute_callable: {
@@ -240,27 +226,22 @@ brw_nir_lower_shader_calls(nir_shader *shader)
nir_iadd(b, nir_load_callable_sbt_addr_intel(b), nir_iadd(b, nir_load_callable_sbt_addr_intel(b),
nir_u2u64(b, sbt_offset32)); nir_u2u64(b, sbt_offset32));
brw_nir_btd_spawn(b, sbt_addr); brw_nir_btd_spawn(b, sbt_addr);
break; return true;
} }
default: default:
unreachable("Invalid intrinsic"); return false;
}
nir_instr_remove(&call->instr);
} }
} }
nir_foreach_block_safe(block, impl) { bool
nir_foreach_instr_safe(instr, block) { brw_nir_lower_shader_calls(nir_shader *shader)
if (instr->type != nir_instr_type_intrinsic) {
continue; return nir_shader_instructions_pass(shader,
lower_shader_calls_instr,
nir_metadata_block_index |
} nir_metadata_dominance,
} NULL);
return progress;
} }
/** Creates a trivial return shader /** Creates a trivial return shader