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radv: Use vk_image as the base for radv_image

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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16376>
This commit is contained in:
Jason Ekstrand
2022-03-25 14:58:39 -05:00
committed by Marge Bot
parent 992690e483
commit c56f3dcbaa
23 changed files with 212 additions and 217 deletions
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4
src/amd/vulkan/radv_android.c
View File

@@ -778,8 +778,8 @@ radv_create_ahb_memory(struct radv_device *device, struct radv_device_memory *me
w = image->info.width;
h = image->info.height;
layers = image->info.array_size;
format = android_format_from_vk(image->vk_format);
usage = radv_ahb_usage_from_vk_usage(image->flags, image->usage);
format = android_format_from_vk(image->vk.format);
usage = radv_ahb_usage_from_vk_usage(image->vk.create_flags, image->vk.usage);
} else if (dedicated_info && dedicated_info->buffer) {
RADV_FROM_HANDLE(radv_buffer, buffer, dedicated_info->buffer);
w = buffer->size;

22
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -2188,7 +2188,7 @@ radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, const struct rad
{
struct radeon_cmdbuf *cs = cmd_buffer->cs;
const struct radv_image *image = iview->image;
VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
VkImageAspectFlags aspects = vk_format_aspects(image->vk.format);
uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
unsigned reg_offset = 0, reg_count = 0;
@@ -2583,7 +2583,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(image),
.viewType = radv_meta_get_view_type(image),
.format = image->vk_format,
.format = image->vk.format,
.subresourceRange =
{
.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT,
@@ -3975,8 +3975,8 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2 src_fla
/* since the STORAGE bit isn't set we know that this is a meta operation.
* on the dst flush side we skip CB/DB flushes without the STORAGE bit, so
* set it here. */
if (image && !(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
if (vk_format_is_depth_or_stencil(image->vk_format)) {
if (image && !(image->vk.usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
if (vk_format_is_depth_or_stencil(image->vk.format)) {
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
} else {
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
@@ -4042,7 +4042,7 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2 dst_fla
bool image_is_coherent = image ? image->l2_coherent : false;
if (image) {
if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
if (!(image->vk.usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
flush_CB = false;
flush_DB = false;
}
@@ -4312,7 +4312,7 @@ radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
uint32_t att_idx = att_sample_locs->attachmentIndex;
struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
assert(vk_format_is_depth_or_stencil(image->vk_format));
assert(vk_format_is_depth_or_stencil(image->vk.format));
/* From the Vulkan spec 1.1.108:
*
@@ -4322,7 +4322,7 @@ radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
* then the values specified in sampleLocationsInfo are
* ignored."
*/
if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
if (!(image->vk.create_flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
continue;
const VkSampleLocationsInfoEXT *sample_locs_info = &att_sample_locs->sampleLocationsInfo;
@@ -8311,7 +8311,7 @@ radv_retile_transition(struct radv_cmd_buffer *cmd_buffer, struct radv_image *im
VkImageLayout src_layout, VkImageLayout dst_layout, unsigned dst_queue_mask)
{
/* If the image is read-only, we don't have to retile DCC because it can't change. */
if (!(image->usage & RADV_IMAGE_USAGE_WRITE_BITS))
if (!(image->vk.usage & RADV_IMAGE_USAGE_WRITE_BITS))
return;
if (src_layout != VK_IMAGE_LAYOUT_PRESENT_SRC_KHR &&
@@ -8383,7 +8383,7 @@ radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer, struct ra
/* MSAA color decompress. */
if (radv_image_has_fmask(image) &&
(image->usage & (VK_IMAGE_USAGE_STORAGE_BIT | VK_IMAGE_USAGE_TRANSFER_DST_BIT)) &&
(image->vk.usage & (VK_IMAGE_USAGE_STORAGE_BIT | VK_IMAGE_USAGE_TRANSFER_DST_BIT)) &&
radv_layout_fmask_compressed(cmd_buffer->device, image, src_layout, src_queue_mask) &&
!radv_layout_fmask_compressed(cmd_buffer->device, image, dst_layout, dst_queue_mask)) {
if (radv_dcc_enabled(image, range->baseMipLevel) &&
@@ -8445,7 +8445,7 @@ radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer, struct radv_ima
if (src_layout == dst_layout && src_render_loop == dst_render_loop && src_queue_mask == dst_queue_mask)
return;
if (vk_format_has_depth(image->vk_format)) {
if (vk_format_has_depth(image->vk.format)) {
radv_handle_depth_image_transition(cmd_buffer, image, src_layout, src_render_loop, dst_layout,
dst_render_loop, src_queue_mask, dst_queue_mask, range,
sample_locs);
@@ -8521,7 +8521,7 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer, const VkDependencyInfo *dep_inf
struct radv_sample_locations_state sample_locations;
if (sample_locs_info) {
assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
assert(image->vk.create_flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
sample_locations.count = sample_locs_info->sampleLocationsCount;

34
src/amd/vulkan/radv_device.c
View File

@@ -4383,7 +4383,7 @@ radv_sparse_image_bind_memory(struct radv_device *device, const VkSparseImageMem
{
RADV_FROM_HANDLE(radv_image, image, bind->image);
struct radeon_surf *surface = &image->planes[0].surface;
uint32_t bs = vk_format_get_blocksize(image->vk_format);
uint32_t bs = vk_format_get_blocksize(image->vk.format);
VkResult result;
for (uint32_t i = 0; i < bind->bindCount; ++i) {
@@ -4395,13 +4395,13 @@ radv_sparse_image_bind_memory(struct radv_device *device, const VkSparseImageMem
VkExtent3D bind_extent = bind->pBinds[i].extent;
bind_extent.width =
DIV_ROUND_UP(bind_extent.width, vk_format_get_blockwidth(image->vk_format));
DIV_ROUND_UP(bind_extent.width, vk_format_get_blockwidth(image->vk.format));
bind_extent.height =
DIV_ROUND_UP(bind_extent.height, vk_format_get_blockheight(image->vk_format));
DIV_ROUND_UP(bind_extent.height, vk_format_get_blockheight(image->vk.format));
VkOffset3D bind_offset = bind->pBinds[i].offset;
bind_offset.x /= vk_format_get_blockwidth(image->vk_format);
bind_offset.y /= vk_format_get_blockheight(image->vk_format);
bind_offset.x /= vk_format_get_blockwidth(image->vk.format);
bind_offset.y /= vk_format_get_blockheight(image->vk.format);
if (bind->pBinds[i].memory != VK_NULL_HANDLE)
mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
@@ -4926,8 +4926,8 @@ radv_alloc_memory(struct radv_device *device, const VkMemoryAllocateInfo *pAlloc
}
if (mem->image && mem->image->plane_count == 1 &&
!vk_format_is_depth_or_stencil(mem->image->vk_format) && mem->image->info.samples == 1 &&
mem->image->tiling != VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) {
!vk_format_is_depth_or_stencil(mem->image->vk.format) && mem->image->info.samples == 1 &&
mem->image->vk.tiling != VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) {
struct radeon_bo_metadata metadata;
device->ws->buffer_get_metadata(device->ws, mem->bo, &metadata);
@@ -5158,7 +5158,7 @@ radv_GetImageMemoryRequirements2(VkDevice _device, const VkImageMemoryRequiremen
case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
VkMemoryDedicatedRequirements *req = (VkMemoryDedicatedRequirements *)ext;
req->requiresDedicatedAllocation =
image->shareable && image->tiling != VK_IMAGE_TILING_LINEAR;
image->shareable && image->vk.tiling != VK_IMAGE_TILING_LINEAR;
req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
break;
}
@@ -5544,7 +5544,7 @@ radv_init_dcc_control_reg(struct radv_device *device, struct radv_image_view *iv
} else {
independent_128b_blocks = 0;
if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
if (iview->image->vk.usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
/* If this DCC image is potentially going to be used in texture
* fetches, we need some special settings.
@@ -5778,13 +5778,13 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
}
if (device->physical_device->rad_info.gfx_level >= GFX9) {
unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D
unsigned mip0_depth = iview->image->vk.image_type == VK_IMAGE_TYPE_3D
? (iview->extent.depth - 1)
: (iview->image->info.array_size - 1);
unsigned width =
vk_format_get_plane_width(iview->image->vk_format, iview->plane_id, iview->extent.width);
vk_format_get_plane_width(iview->image->vk.format, iview->plane_id, iview->extent.width);
unsigned height =
vk_format_get_plane_height(iview->image->vk_format, iview->plane_id, iview->extent.height);
vk_format_get_plane_height(iview->image->vk.format, iview->plane_id, iview->extent.height);
if (device->physical_device->rad_info.gfx_level >= GFX10) {
cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
@@ -5854,7 +5854,7 @@ radv_initialise_vrs_surface(struct radv_image *image, struct radv_buffer *htile_
{
const struct radeon_surf *surf = &image->planes[0].surface;
assert(image->vk_format == VK_FORMAT_D16_UNORM);
assert(image->vk.format == VK_FORMAT_D16_UNORM);
memset(ds, 0, sizeof(*ds));
ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
@@ -5880,15 +5880,15 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf
unsigned level = iview->base_mip;
unsigned format, stencil_format;
uint64_t va, s_offs, z_offs;
bool stencil_only = iview->image->vk_format == VK_FORMAT_S8_UINT;
bool stencil_only = iview->image->vk.format == VK_FORMAT_S8_UINT;
const struct radv_image_plane *plane = &iview->image->planes[0];
const struct radeon_surf *surf = &plane->surface;
assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
assert(vk_format_get_plane_count(iview->image->vk.format) == 1);
memset(ds, 0, sizeof(*ds));
if (!device->instance->absolute_depth_bias) {
switch (iview->image->vk_format) {
switch (iview->image->vk.format) {
case VK_FORMAT_D24_UNORM_S8_UINT:
case VK_FORMAT_X8_D24_UNORM_PACK32:
ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
@@ -5907,7 +5907,7 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf
}
}
format = radv_translate_dbformat(iview->image->vk_format);
format = radv_translate_dbformat(iview->image->vk.format);
stencil_format = surf->has_stencil ? V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;

4
src/amd/vulkan/radv_formats.c
View File

@@ -1941,7 +1941,7 @@ radv_GetImageSparseMemoryRequirements2(VkDevice _device,
RADV_FROM_HANDLE(radv_device, device, _device);
RADV_FROM_HANDLE(radv_image, image, pInfo->image);
if (!(image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)) {
if (!(image->vk.create_flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)) {
*pSparseMemoryRequirementCount = 0;
return;
}
@@ -1951,7 +1951,7 @@ radv_GetImageSparseMemoryRequirements2(VkDevice _device,
vk_outarray_append_typed(VkSparseImageMemoryRequirements2, &out, req)
{
fill_sparse_image_format_properties(device->physical_device, image->vk_format,
fill_sparse_image_format_properties(device->physical_device, image->vk.format,
&req->memoryRequirements.formatProperties);
req->memoryRequirements.imageMipTailFirstLod = image->planes[0].surface.first_mip_tail_level;

146
src/amd/vulkan/radv_image.c
View File

@@ -135,7 +135,7 @@ radv_image_use_fast_clear_for_image_early(const struct radv_device *device,
return false;
}
return !!(image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT);
return !!(image->vk.usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT);
}
static bool
@@ -236,7 +236,7 @@ radv_use_dcc_for_image_early(struct radv_device *device, struct radv_image *imag
if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
return false;
if (image->shareable && image->tiling != VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT)
if (image->shareable && image->vk.tiling != VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT)
return false;
/*
@@ -262,7 +262,7 @@ radv_use_dcc_for_image_early(struct radv_device *device, struct radv_image *imag
return false;
if (!radv_image_use_fast_clear_for_image_early(device, image) &&
image->tiling != VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT)
image->vk.tiling != VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT)
return false;
/* Do not enable DCC for mipmapped arrays because performance is worse. */
@@ -290,7 +290,7 @@ radv_use_dcc_for_image_late(struct radv_device *device, struct radv_image *image
if (!radv_image_has_dcc(image))
return false;
if (image->tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT)
if (image->vk.tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT)
return true;
if (!radv_image_use_fast_clear_for_image(device, image))
@@ -298,7 +298,8 @@ radv_use_dcc_for_image_late(struct radv_device *device, struct radv_image *image
/* TODO: Fix storage images with DCC without DCC image stores.
* Disabling it for now. */
if ((image->usage & VK_IMAGE_USAGE_STORAGE_BIT) && !radv_image_use_dcc_image_stores(device, image))
if ((image->vk.usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
!radv_image_use_dcc_image_stores(device, image))
return false;
return true;
@@ -334,7 +335,7 @@ radv_image_use_dcc_predication(const struct radv_device *device, const struct ra
static inline bool
radv_use_fmask_for_image(const struct radv_device *device, const struct radv_image *image)
{
return image->info.samples > 1 && ((image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) ||
return image->info.samples > 1 && ((image->vk.usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) ||
(device->instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS));
}
@@ -350,7 +351,7 @@ radv_use_htile_for_image(const struct radv_device *device, const struct radv_ima
/* Stencil texturing with HTILE doesn't work with mipmapping on Navi10-14. */
if (device->physical_device->rad_info.gfx_level == GFX10 &&
image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT && image->info.levels > 1)
image->vk.format == VK_FORMAT_D32_SFLOAT_S8_UINT && image->info.levels > 1)
return false;
/* Do not enable HTILE for very small images because it seems less performant but make sure it's
@@ -378,14 +379,14 @@ radv_use_tc_compat_cmask_for_image(struct radv_device *device, struct radv_image
return false;
/* TC-compat CMASK with storage images is supported on GFX10+. */
if ((image->usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
if ((image->vk.usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
device->physical_device->rad_info.gfx_level < GFX10)
return false;
/* Do not enable TC-compatible if the image isn't readable by a shader
* because no texture fetches will happen.
*/
if (!(image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT |
if (!(image->vk.usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT |
VK_IMAGE_USAGE_TRANSFER_SRC_BIT)))
return false;
@@ -566,12 +567,12 @@ radv_image_get_plane_format(const struct radv_physical_device *pdev, const struc
unsigned plane)
{
if (pdev->emulate_etc2 &&
vk_format_description(image->vk_format)->layout == UTIL_FORMAT_LAYOUT_ETC) {
vk_format_description(image->vk.format)->layout == UTIL_FORMAT_LAYOUT_ETC) {
if (plane == 0)
return image->vk_format;
return etc2_emulation_format(image->vk_format);
return image->vk.format;
return etc2_emulation_format(image->vk.format);
}
return vk_format_get_plane_format(image->vk_format, plane);
return vk_format_get_plane_format(image->vk.format, plane);
}
static uint64_t
@@ -965,10 +966,10 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima
/* For emulated ETC2 without alpha we need to override the format to a 3-componenent format, so
* that border colors work correctly (alpha forced to 1). Since Vulkan has no such format,
* this uses the Gallium formats to set the description. */
if (image->vk_format == VK_FORMAT_ETC2_R8G8B8_UNORM_BLOCK &&
if (image->vk.format == VK_FORMAT_ETC2_R8G8B8_UNORM_BLOCK &&
vk_format == VK_FORMAT_R8G8B8A8_UNORM) {
desc = util_format_description(PIPE_FORMAT_R8G8B8X8_UNORM);
} else if (image->vk_format == VK_FORMAT_ETC2_R8G8B8_SRGB_BLOCK &&
} else if (image->vk.format == VK_FORMAT_ETC2_R8G8B8_SRGB_BLOCK &&
vk_format == VK_FORMAT_R8G8B8A8_SRGB) {
desc = util_format_description(PIPE_FORMAT_R8G8B8X8_SRGB);
}
@@ -978,10 +979,10 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima
radv_compose_swizzle(desc, mapping, swizzle);
if (img_create_flags & VK_IMAGE_CREATE_2D_VIEW_COMPATIBLE_BIT_EXT) {
assert(image->type == VK_IMAGE_TYPE_3D);
assert(image->vk.image_type == VK_IMAGE_TYPE_3D);
type = V_008F1C_SQ_RSRC_IMG_3D;
} else {
type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
type = radv_tex_dim(image->vk.image_type, view_type, image->info.array_size, image->info.samples,
is_storage_image, device->physical_device->rad_info.gfx_level == GFX9);
}
@@ -1085,7 +1086,7 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima
S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) | S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.color.fmask_swizzle_mode) |
S_00A00C_TYPE(
radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
radv_tex_dim(image->vk.image_type, view_type, image->info.array_size, 0, false, false));
fmask_state[4] = S_00A010_DEPTH(last_layer) | S_00A010_BASE_ARRAY(first_layer);
fmask_state[5] = 0;
fmask_state[6] = S_00A018_META_PIPE_ALIGNED(1);
@@ -1125,10 +1126,10 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image,
/* For emulated ETC2 without alpha we need to override the format to a 3-componenent format, so
* that border colors work correctly (alpha forced to 1). Since Vulkan has no such format,
* this uses the Gallium formats to set the description. */
if (image->vk_format == VK_FORMAT_ETC2_R8G8B8_UNORM_BLOCK &&
if (image->vk.format == VK_FORMAT_ETC2_R8G8B8_UNORM_BLOCK &&
vk_format == VK_FORMAT_R8G8B8A8_UNORM) {
desc = util_format_description(PIPE_FORMAT_R8G8B8X8_UNORM);
} else if (image->vk_format == VK_FORMAT_ETC2_R8G8B8_SRGB_BLOCK &&
} else if (image->vk.format == VK_FORMAT_ETC2_R8G8B8_SRGB_BLOCK &&
vk_format == VK_FORMAT_R8G8B8A8_SRGB) {
desc = util_format_description(PIPE_FORMAT_R8G8B8X8_SRGB);
}
@@ -1150,18 +1151,18 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image,
/* S8 with either Z16 or Z32 HTILE need a special format. */
if (device->physical_device->rad_info.gfx_level == GFX9 && vk_format == VK_FORMAT_S8_UINT &&
radv_image_is_tc_compat_htile(image)) {
if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
if (image->vk.format == VK_FORMAT_D32_SFLOAT_S8_UINT)
data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
else if (image->vk.format == VK_FORMAT_D16_UNORM_S8_UINT)
data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
}
if (device->physical_device->rad_info.gfx_level == GFX9 &&
img_create_flags & VK_IMAGE_CREATE_2D_VIEW_COMPATIBLE_BIT_EXT) {
assert(image->type == VK_IMAGE_TYPE_3D);
assert(image->vk.image_type == VK_IMAGE_TYPE_3D);
type = V_008F1C_SQ_RSRC_IMG_3D;
} else {
type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
type = radv_tex_dim(image->vk.image_type, view_type, image->info.array_size, image->info.samples,
is_storage_image, device->physical_device->rad_info.gfx_level == GFX9);
}
@@ -1281,7 +1282,7 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image,
S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) | S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) | S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
S_008F1C_TYPE(
radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
radv_tex_dim(image->vk.image_type, view_type, image->info.array_size, 0, false, false));
fmask_state[4] = 0;
fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
fmask_state[6] = 0;
@@ -1348,8 +1349,8 @@ radv_query_opaque_metadata(struct radv_device *device, struct radv_image *image,
assert(image->plane_count == 1);
radv_make_texture_descriptor(device, image, false, (VkImageViewType)image->type,
image->vk_format, &fixedmapping, 0, image->info.levels - 1, 0,
radv_make_texture_descriptor(device, image, false, (VkImageViewType)image->vk.image_type,
image->vk.format, &fixedmapping, 0, image->info.levels - 1, 0,
image->info.array_size - 1, image->info.width, image->info.height,
image->info.depth, 0.0f, desc, NULL, 0);
@@ -1415,7 +1416,7 @@ radv_image_alloc_single_sample_cmask(const struct radv_device *device,
if (!surf->cmask_size || surf->cmask_offset || surf->bpe > 8 || image->info.levels > 1 ||
image->info.depth > 1 || radv_image_has_dcc(image) ||
!radv_image_use_fast_clear_for_image(device, image) ||
(image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT))
(image->vk.create_flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT))
return;
assert(image->info.storage_samples == 1);
@@ -1429,7 +1430,7 @@ static void
radv_image_alloc_values(const struct radv_device *device, struct radv_image *image)
{
/* images with modifiers can be potentially imported */
if (image->tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT)
if (image->vk.tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT)
return;
if (radv_image_has_cmask(image) || (radv_image_has_dcc(image) && !image->support_comp_to_single)) {
@@ -1478,7 +1479,7 @@ radv_image_is_pipe_misaligned(const struct radv_device *device, const struct rad
if (rad_info->gfx_level >= GFX10_3) {
log2_bpp_and_samples = log2_bpp + log2_samples;
} else {
if (vk_format_has_depth(image->vk_format) && image->info.array_size >= 8) {
if (vk_format_has_depth(image->vk.format) && image->info.array_size >= 8) {
log2_bpp = 2;
}
@@ -1488,7 +1489,7 @@ radv_image_is_pipe_misaligned(const struct radv_device *device, const struct rad
int num_pipes = G_0098F8_NUM_PIPES(rad_info->gb_addr_config);
int overlap = MAX2(0, log2_bpp_and_samples + num_pipes - 8);
if (vk_format_has_depth(image->vk_format)) {
if (vk_format_has_depth(image->vk.format)) {
if (radv_image_is_tc_compat_htile(image) && overlap) {
return true;
}
@@ -1518,9 +1519,9 @@ radv_image_is_l2_coherent(const struct radv_device *device, const struct radv_im
!radv_image_is_pipe_misaligned(device, image);
} else if (device->physical_device->rad_info.gfx_level == GFX9) {
if (image->info.samples == 1 &&
(image->usage &
(image->vk.usage &
(VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT | VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
!vk_format_has_stencil(image->vk_format)) {
!vk_format_has_stencil(image->vk.format)) {
/* Single-sample color and single-sample depth
* (not stencil) are coherent with shaders on
* GFX9.
@@ -1541,7 +1542,7 @@ radv_image_can_fast_clear(const struct radv_device *device, const struct radv_im
if (device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
return false;
if (vk_format_is_color(image->vk_format)) {
if (vk_format_is_color(image->vk.format)) {
if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
return false;
@@ -1554,7 +1555,7 @@ radv_image_can_fast_clear(const struct radv_device *device, const struct radv_im
}
/* Do not fast clears 3D images. */
if (image->type == VK_IMAGE_TYPE_3D)
if (image->vk.image_type == VK_IMAGE_TYPE_3D)
return false;
return true;
@@ -1579,7 +1580,7 @@ radv_image_use_comp_to_single(const struct radv_device *device, const struct rad
return false;
/* It seems 8bpp and 16bpp require RB+ to work. */
unsigned bytes_per_pixel = vk_format_get_blocksize(image->vk_format);
unsigned bytes_per_pixel = vk_format_get_blocksize(image->vk.format);
if (bytes_per_pixel <= 2 && !device->physical_device->rad_info.rbplus_allowed)
return false;
@@ -1604,7 +1605,7 @@ radv_image_reset_layout(const struct radv_physical_device *pdev, struct radv_ima
image->fce_pred_offset = image->dcc_pred_offset = 0;
image->clear_value_offset = image->tc_compat_zrange_offset = 0;
unsigned plane_count = radv_get_internal_plane_count(pdev, image->vk_format);
unsigned plane_count = radv_get_internal_plane_count(pdev, image->vk.format);
for (unsigned i = 0; i < plane_count; ++i) {
VkFormat format = radv_image_get_plane_format(pdev, image, i);
if (vk_format_has_depth(format))
@@ -1645,14 +1646,14 @@ radv_image_create_layout(struct radv_device *device, struct radv_image_create_in
radv_image_reset_layout(device->physical_device, image);
unsigned plane_count = radv_get_internal_plane_count(device->physical_device, image->vk_format);
unsigned plane_count = radv_get_internal_plane_count(device->physical_device, image->vk.format);
for (unsigned plane = 0; plane < plane_count; ++plane) {
struct ac_surf_info info = image_info;
uint64_t offset;
unsigned stride;
info.width = vk_format_get_plane_width(image->vk_format, plane, info.width);
info.height = vk_format_get_plane_height(image->vk_format, plane, info.height);
info.width = vk_format_get_plane_width(image->vk.format, plane, info.width);
info.height = vk_format_get_plane_height(image->vk.format, plane, info.height);
if (create_info.no_metadata_planes || plane_count > 1) {
image->planes[plane].surface.flags |=
@@ -1734,7 +1735,7 @@ static void
radv_destroy_image(struct radv_device *device, const VkAllocationCallbacks *pAllocator,
struct radv_image *image)
{
if ((image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) && image->bo)
if ((image->vk.create_flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) && image->bo)
device->ws->buffer_destroy(device->ws, image->bo);
if (image->owned_memory != VK_NULL_HANDLE) {
@@ -1742,7 +1743,7 @@ radv_destroy_image(struct radv_device *device, const VkAllocationCallbacks *pAll
radv_free_memory(device, pAllocator, mem);
}
vk_object_base_finish(&image->base);
vk_image_finish(&image->vk);
vk_free2(&device->vk.alloc, pAllocator, image);
}
@@ -1839,9 +1840,8 @@ radv_image_create(VkDevice _device, const struct radv_image_create_info *create_
if (!image)
return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
vk_object_base_init(&device->vk, &image->base, VK_OBJECT_TYPE_IMAGE);
vk_image_init(&device->vk, &image->vk, pCreateInfo);
image->type = pCreateInfo->imageType;
image->info.width = pCreateInfo->extent.width;
image->info.height = pCreateInfo->extent.height;
image->info.depth = pCreateInfo->extent.depth;
@@ -1851,10 +1851,6 @@ radv_image_create(VkDevice _device, const struct radv_image_create_info *create_
image->info.levels = pCreateInfo->mipLevels;
image->info.num_channels = vk_format_get_nr_components(format);
image->vk_format = format;
image->tiling = pCreateInfo->tiling;
image->usage = pCreateInfo->usage;
image->flags = pCreateInfo->flags;
image->plane_count = vk_format_get_plane_count(format);
image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
@@ -1873,7 +1869,7 @@ radv_image_create(VkDevice _device, const struct radv_image_create_info *create_
image->shareable = external_info;
if (!vk_format_is_depth_or_stencil(format) && !image->shareable &&
!(image->flags & VK_IMAGE_CREATE_SPARSE_ALIASED_BIT) &&
!(image->vk.create_flags & VK_IMAGE_CREATE_SPARSE_ALIASED_BIT) &&
pCreateInfo->tiling != VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) {
image->info.surf_index = &device->image_mrt_offset_counter;
}
@@ -1895,7 +1891,7 @@ radv_image_create(VkDevice _device, const struct radv_image_create_info *create_
if (delay_layout) {
*pImage = radv_image_to_handle(image);
assert(!(image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT));
assert(!(image->vk.create_flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT));
return VK_SUCCESS;
}
@@ -1905,7 +1901,7 @@ radv_image_create(VkDevice _device, const struct radv_image_create_info *create_
return result;
}
if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
if (image->vk.create_flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
image->alignment = MAX2(image->alignment, 4096);
image->size = align64(image->size, image->alignment);
image->offset = 0;
@@ -1960,8 +1956,8 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, struct radv_devic
device, image, is_storage_image, iview->type, vk_format, components, hw_level,
hw_level + iview->level_count - 1, iview->base_layer,
iview->base_layer + iview->layer_count - 1,
vk_format_get_plane_width(image->vk_format, plane_id, iview->extent.width),
vk_format_get_plane_height(image->vk_format, plane_id, iview->extent.height),
vk_format_get_plane_width(image->vk.format, plane_id, iview->extent.width),
vk_format_get_plane_height(image->vk.format, plane_id, iview->extent.height),
iview->extent.depth, min_lod, descriptor->plane_descriptors[descriptor_plane_id],
descriptor_plane_id || is_storage_image ? NULL : descriptor->fmask_descriptor,
img_create_flags);
@@ -2011,13 +2007,13 @@ radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask)
case VK_IMAGE_ASPECT_PLANE_2_BIT:
return image->planes[2].format;
case VK_IMAGE_ASPECT_STENCIL_BIT:
return vk_format_stencil_only(image->vk_format);
return vk_format_stencil_only(image->vk.format);
case VK_IMAGE_ASPECT_DEPTH_BIT:
return vk_format_depth_only(image->vk_format);
return vk_format_depth_only(image->vk.format);
case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
return vk_format_depth_only(image->vk_format);
return vk_format_depth_only(image->vk.format);
default:
return image->vk_format;
return image->vk.format;
}
}
@@ -2068,7 +2064,7 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device,
vk_object_base_init(&device->vk, &iview->base, VK_OBJECT_TYPE_IMAGE_VIEW);
switch (image->type) {
switch (image->vk.image_type) {
case VK_IMAGE_TYPE_1D:
case VK_IMAGE_TYPE_2D:
assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <=
@@ -2095,7 +2091,7 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device,
/* If the image has an Android external format, pCreateInfo->format will be
* VK_FORMAT_UNDEFINED. */
if (iview->vk_format == VK_FORMAT_UNDEFINED)
iview->vk_format = image->vk_format;
iview->vk_format = image->vk.format;
/* Split out the right aspect. Note that for internal meta code we sometimes
* use an equivalent color format for the aspect so we first have to check
@@ -2108,13 +2104,13 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device,
iview->vk_format = vk_format_depth_only(iview->vk_format);
}
if (vk_format_get_plane_count(image->vk_format) > 1 &&
if (vk_format_get_plane_count(image->vk.format) > 1 &&
iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT) {
plane_count = vk_format_get_plane_count(iview->vk_format);
}
if (device->physical_device->emulate_etc2 &&
vk_format_description(image->vk_format)->layout == UTIL_FORMAT_LAYOUT_ETC) {
vk_format_description(image->vk.format)->layout == UTIL_FORMAT_LAYOUT_ETC) {
const struct util_format_description *desc = vk_format_description(iview->vk_format);
assert(desc);
if (desc->layout == UTIL_FORMAT_LAYOUT_ETC) {
@@ -2175,7 +2171,7 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device,
* the plain converted dimensions the physical layout is correct.
*/
if (device->physical_device->rad_info.gfx_level >= GFX9 &&
vk_format_is_compressed(image->vk_format) && !vk_format_is_compressed(iview->vk_format)) {
vk_format_is_compressed(image->vk.format) && !vk_format_is_compressed(iview->vk_format)) {
/* If we have multiple levels in the view we should ideally take the last level,
* but the mip calculation has a max(..., 1) so walking back to the base mip in an
* useful way is hard. */
@@ -2256,7 +2252,8 @@ radv_layout_is_htile_compressed(const struct radv_device *device, const struct r
case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL:
if (radv_image_is_tc_compat_htile(image) ||
(radv_image_has_htile(image) &&
!(image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)))) {
!(image->vk.usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)))) {
/* Keep HTILE compressed if the image is only going to
* be used as a depth/stencil read-only attachment.
*/
@@ -2279,7 +2276,7 @@ radv_layout_can_fast_clear(const struct radv_device *device, const struct radv_i
!radv_layout_dcc_compressed(device, image, level, layout, in_render_loop, queue_mask))
return false;
if (!(image->usage & RADV_IMAGE_USAGE_WRITE_BITS))
if (!(image->vk.usage & RADV_IMAGE_USAGE_WRITE_BITS))
return false;
if (layout != VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
@@ -2301,11 +2298,12 @@ radv_layout_dcc_compressed(const struct radv_device *device, const struct radv_i
if (!radv_dcc_enabled(image, level))
return false;
if (image->tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT && queue_mask & (1u << RADV_QUEUE_FOREIGN))
if (image->vk.tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT &&
queue_mask & (1u << RADV_QUEUE_FOREIGN))
return true;
/* If the image is read-only, we can always just keep it compressed */
if (!(image->usage & RADV_IMAGE_USAGE_WRITE_BITS))
if (!(image->vk.usage & RADV_IMAGE_USAGE_WRITE_BITS))
return true;
/* Don't compress compute transfer dst when image stores are not supported. */
@@ -2397,13 +2395,13 @@ radv_GetImageSubresourceLayout(VkDevice _device, VkImage _image,
int layer = pSubresource->arrayLayer;
unsigned plane_id = 0;
if (vk_format_get_plane_count(image->vk_format) > 1)
if (vk_format_get_plane_count(image->vk.format) > 1)
plane_id = radv_plane_from_aspect(pSubresource->aspectMask);
struct radv_image_plane *plane = &image->planes[plane_id];
struct radeon_surf *surface = &plane->surface;
if (image->tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) {
if (image->vk.tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) {
unsigned mem_plane_id = radv_plane_from_aspect(pSubresource->aspectMask);
assert(level == 0);
@@ -2422,9 +2420,9 @@ radv_GetImageSubresourceLayout(VkDevice _device, VkImage _image,
pLayout->offset = ac_surface_get_plane_offset(device->physical_device->rad_info.gfx_level,
&plane->surface, 0, layer) +
level_offset;
if (image->vk_format == VK_FORMAT_R32G32B32_UINT ||
image->vk_format == VK_FORMAT_R32G32B32_SINT ||
image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) {
if (image->vk.format == VK_FORMAT_R32G32B32_UINT ||
image->vk.format == VK_FORMAT_R32G32B32_SINT ||
image->vk.format == VK_FORMAT_R32G32B32_SFLOAT) {
/* Adjust the number of bytes between each row because
* the pitch is actually the number of components per
* row.
@@ -2441,7 +2439,7 @@ radv_GetImageSubresourceLayout(VkDevice _device, VkImage _image,
pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
pLayout->size = surface->u.gfx9.surf_slice_size;
if (image->type == VK_IMAGE_TYPE_3D)
if (image->vk.image_type == VK_IMAGE_TYPE_3D)
pLayout->size *= u_minify(image->info.depth, level);
} else {
pLayout->offset = (uint64_t)surface->u.legacy.level[level].offset_256B * 256 +
@@ -2450,7 +2448,7 @@ radv_GetImageSubresourceLayout(VkDevice _device, VkImage _image,
pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
if (image->type == VK_IMAGE_TYPE_3D)
if (image->vk.image_type == VK_IMAGE_TYPE_3D)
pLayout->size *= u_minify(image->info.depth, level);
}
}
@@ -2478,7 +2476,7 @@ radv_CreateImageView(VkDevice _device, const VkImageViewCreateInfo *pCreateInfo,
if (view == NULL)
return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
radv_image_view_init(view, device, pCreateInfo, image->flags, NULL);
radv_image_view_init(view, device, pCreateInfo, image->vk.create_flags, NULL);
*pView = radv_image_view_to_handle(view);

4
src/amd/vulkan/radv_meta.c
View File

@@ -349,7 +349,7 @@ radv_meta_restore(const struct radv_meta_saved_state *state, struct radv_cmd_buf
VkImageViewType
radv_meta_get_view_type(const struct radv_image *image)
{
switch (image->type) {
switch (image->vk.image_type) {
case VK_IMAGE_TYPE_1D:
return VK_IMAGE_VIEW_TYPE_1D;
case VK_IMAGE_TYPE_2D:
@@ -370,7 +370,7 @@ radv_meta_get_iview_layer(const struct radv_image *dest_image,
const VkImageSubresourceLayers *dest_subresource,
const VkOffset3D *dest_offset)
{
switch (dest_image->type) {
switch (dest_image->vk.image_type) {
case VK_IMAGE_TYPE_1D:
case VK_IMAGE_TYPE_2D:
return dest_subresource->baseArrayLayer;

23
src/amd/vulkan/radv_meta_blit.c
View File

@@ -273,7 +273,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
case VK_IMAGE_ASPECT_COLOR_BIT: {
unsigned dst_layout = radv_meta_dst_layout_from_layout(dest_image_layout);
VkImageLayout layout = radv_meta_dst_layout_to_layout(dst_layout);
fs_key = radv_format_meta_fs_key(device, dest_image->vk_format);
fs_key = radv_format_meta_fs_key(device, dest_image->vk.format);
format = radv_fs_key_format_exemplars[fs_key];
color_att.sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO;
@@ -282,7 +282,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
color_att.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD;
color_att.storeOp = VK_ATTACHMENT_STORE_OP_STORE;
switch (src_image->type) {
switch (src_image->vk.image_type) {
case VK_IMAGE_TYPE_1D:
pipeline = &device->meta_state.blit.pipeline_1d_src[fs_key];
break;
@@ -308,7 +308,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
depth_att.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD;
depth_att.storeOp = VK_ATTACHMENT_STORE_OP_STORE;
switch (src_image->type) {
switch (src_image->vk.image_type) {
case VK_IMAGE_TYPE_1D:
pipeline = &device->meta_state.blit.depth_only_1d_pipeline;
break;
@@ -334,7 +334,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
stencil_att.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD;
stencil_att.storeOp = VK_ATTACHMENT_STORE_OP_STORE;
switch (src_image->type) {
switch (src_image->vk.image_type) {
case VK_IMAGE_TYPE_1D:
pipeline = &device->meta_state.blit.stencil_only_1d_pipeline;
break;
@@ -355,7 +355,8 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
if (!*pipeline) {
VkResult ret = build_pipeline(device, src_iview->aspect_mask,
translate_sampler_dim(src_image->type), format, pipeline);
translate_sampler_dim(src_image->vk.image_type),
format, pipeline);
if (ret != VK_SUCCESS) {
cmd_buffer->record_result = ret;
return;
@@ -489,7 +490,7 @@ blit_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
cmd_buffer->state.predicating = false;
unsigned dst_start, dst_end;
if (dst_image->type == VK_IMAGE_TYPE_3D) {
if (dst_image->vk.image_type == VK_IMAGE_TYPE_3D) {
assert(dst_res->baseArrayLayer == 0);
dst_start = region->dstOffsets[0].z;
dst_end = region->dstOffsets[1].z;
@@ -499,7 +500,7 @@ blit_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
}
unsigned src_start, src_end;
if (src_image->type == VK_IMAGE_TYPE_3D) {
if (src_image->vk.image_type == VK_IMAGE_TYPE_3D) {
assert(src_res->baseArrayLayer == 0);
src_start = region->srcOffsets[0].z;
src_end = region->srcOffsets[1].z;
@@ -514,7 +515,7 @@ blit_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
/* There is no interpolation to the pixel center during
* rendering, so add the 0.5 offset ourselves here. */
float depth_center_offset = 0;
if (src_image->type == VK_IMAGE_TYPE_3D)
if (src_image->vk.image_type == VK_IMAGE_TYPE_3D)
depth_center_offset = 0.5 / (dst_end - dst_start) * (src_end - src_start);
if (flip_z) {
@@ -565,14 +566,14 @@ blit_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
const uint32_t dst_array_slice = dst_start + i;
/* 3D images have just 1 layer */
const uint32_t src_array_slice = src_image->type == VK_IMAGE_TYPE_3D ? 0 : src_start + i;
const uint32_t src_array_slice = src_image->vk.image_type == VK_IMAGE_TYPE_3D ? 0 : src_start + i;
radv_image_view_init(&dst_iview, cmd_buffer->device,
&(VkImageViewCreateInfo){
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(dst_image),
.viewType = radv_meta_get_view_type(dst_image),
.format = dst_image->vk_format,
.format = dst_image->vk.format,
.subresourceRange = {.aspectMask = dst_res->aspectMask,
.baseMipLevel = dst_res->mipLevel,
.levelCount = 1,
@@ -585,7 +586,7 @@ blit_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(src_image),
.viewType = radv_meta_get_view_type(src_image),
.format = src_image->vk_format,
.format = src_image->vk.format,
.subresourceRange = {.aspectMask = src_res->aspectMask,
.baseMipLevel = src_res->mipLevel,
.levelCount = 1,

6
src/amd/vulkan/radv_meta_blit2d.c
View File

@@ -210,9 +210,9 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
unsigned src_aspect_mask = aspect_mask;
VkFormat depth_format = 0;
if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT)
depth_format = vk_format_stencil_only(dst->image->vk_format);
depth_format = vk_format_stencil_only(dst->image->vk.format);
else if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT)
depth_format = vk_format_depth_only(dst->image->vk_format);
depth_format = vk_format_depth_only(dst->image->vk.format);
else if (src_img)
src_aspect_mask = src_img->aspect_mask;
@@ -373,7 +373,7 @@ radv_meta_blit2d(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_sur
struct radv_meta_blit2d_buffer *src_buf, struct radv_meta_blit2d_surf *dst,
unsigned num_rects, struct radv_meta_blit2d_rect *rects)
{
bool use_3d = (src_img && src_img->image->type == VK_IMAGE_TYPE_3D);
bool use_3d = (src_img && src_img->image->vk.image_type == VK_IMAGE_TYPE_3D);
enum blit2d_src_type src_type = src_buf ? BLIT2D_SRC_TYPE_BUFFER
: use_3d ? BLIT2D_SRC_TYPE_IMAGE_3D
: BLIT2D_SRC_TYPE_IMAGE;

19
src/amd/vulkan/radv_meta_bufimage.c
View File

@@ -1380,7 +1380,7 @@ radv_meta_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_b
create_bview(cmd_buffer, dst->buffer, dst->offset, dst->format, &dst_view);
itob_bind_descriptors(cmd_buffer, &src_view, &dst_view);
if (src->image->type == VK_IMAGE_TYPE_3D)
if (src->image->vk.image_type == VK_IMAGE_TYPE_3D)
pipeline = cmd_buffer->device->meta_state.itob.pipeline_3d;
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
@@ -1519,9 +1519,9 @@ radv_meta_buffer_to_image_cs(struct radv_cmd_buffer *cmd_buffer,
struct radv_buffer_view src_view;
struct radv_image_view dst_view;
if (dst->image->vk_format == VK_FORMAT_R32G32B32_UINT ||
dst->image->vk_format == VK_FORMAT_R32G32B32_SINT ||
dst->image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) {
if (dst->image->vk.format == VK_FORMAT_R32G32B32_UINT ||
dst->image->vk.format == VK_FORMAT_R32G32B32_SINT ||
dst->image->vk.format == VK_FORMAT_R32G32B32_SFLOAT) {
radv_meta_buffer_to_image_cs_r32g32b32(cmd_buffer, src, dst, num_rects, rects);
return;
}
@@ -1530,7 +1530,7 @@ radv_meta_buffer_to_image_cs(struct radv_cmd_buffer *cmd_buffer,
create_iview(cmd_buffer, dst, &dst_view, VK_FORMAT_UNDEFINED, dst->aspect_mask);
btoi_bind_descriptors(cmd_buffer, &src_view, &dst_view);
if (dst->image->type == VK_IMAGE_TYPE_3D)
if (dst->image->vk.image_type == VK_IMAGE_TYPE_3D)
pipeline = cmd_buffer->device->meta_state.btoi.pipeline_3d;
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
pipeline);
@@ -1691,9 +1691,9 @@ radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta
unsigned aspect_mask = 1u << i;
VkFormat depth_format = 0;
if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT)
depth_format = vk_format_stencil_only(dst->image->vk_format);
depth_format = vk_format_stencil_only(dst->image->vk.format);
else if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT)
depth_format = vk_format_depth_only(dst->image->vk_format);
depth_format = vk_format_depth_only(dst->image->vk.format);
create_iview(cmd_buffer, src, &src_view, depth_format, aspect_mask);
create_iview(cmd_buffer, dst, &dst_view, depth_format, aspect_mask);
@@ -1701,7 +1701,8 @@ radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta
itoi_bind_descriptors(cmd_buffer, &src_view, &dst_view);
VkPipeline pipeline = cmd_buffer->device->meta_state.itoi.pipeline[samples_log2];
if (src->image->type == VK_IMAGE_TYPE_3D || dst->image->type == VK_IMAGE_TYPE_3D)
if (src->image->vk.image_type == VK_IMAGE_TYPE_3D ||
dst->image->vk.image_type == VK_IMAGE_TYPE_3D)
pipeline = cmd_buffer->device->meta_state.itoi.pipeline_3d;
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
pipeline);
@@ -1828,7 +1829,7 @@ radv_meta_clear_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_bl
cleari_bind_descriptors(cmd_buffer, &dst_iview);
VkPipeline pipeline = cmd_buffer->device->meta_state.cleari.pipeline[samples_log2];
if (dst->image->type == VK_IMAGE_TYPE_3D)
if (dst->image->vk.image_type == VK_IMAGE_TYPE_3D)
pipeline = cmd_buffer->device->meta_state.cleari.pipeline_3d;
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,

8
src/amd/vulkan/radv_meta_clear.c
View File

@@ -1358,7 +1358,7 @@ radv_clear_dcc_comp_to_single(struct radv_cmd_buffer *cmd_buffer,
uint32_t color_values[2])
{
struct radv_device *device = cmd_buffer->device;
unsigned bytes_per_pixel = vk_format_get_blocksize(image->vk_format);
unsigned bytes_per_pixel = vk_format_get_blocksize(image->vk.format);
unsigned layer_count = radv_get_layerCount(image, range);
struct radv_meta_saved_state saved_state;
bool is_msaa = image->info.samples > 1;
@@ -2160,7 +2160,7 @@ radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer, struct radv_image *ima
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(image),
.viewType = radv_meta_get_view_type(image),
.format = image->vk_format,
.format = image->vk.format,
.subresourceRange =
{
.aspectMask = range->aspectMask,
@@ -2217,7 +2217,7 @@ radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *imag
VkImageLayout image_layout, const VkClearValue *clear_value,
uint32_t range_count, const VkImageSubresourceRange *ranges, bool cs)
{
VkFormat format = image->vk_format;
VkFormat format = image->vk.format;
VkClearValue internal_clear_value;
if (ranges->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT)
@@ -2271,7 +2271,7 @@ radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *imag
}
for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D
const uint32_t layer_count = image->vk.image_type == VK_IMAGE_TYPE_3D
? radv_minify(image->info.depth, range->baseMipLevel + l)
: radv_get_layerCount(image, range);

48
src/amd/vulkan/radv_meta_copy.c
View File

@@ -27,7 +27,7 @@
static VkExtent3D
meta_image_block_size(const struct radv_image *image)
{
const struct util_format_description *desc = vk_format_description(image->vk_format);
const struct util_format_description *desc = vk_format_description(image->vk.format);
return (VkExtent3D){desc->block.width, desc->block.height, 1};
}
@@ -56,7 +56,8 @@ static struct VkOffset3D
meta_region_offset_el(const struct radv_image *image, const struct VkOffset3D *offset)
{
const VkExtent3D block = meta_image_block_size(image);
return radv_sanitize_image_offset(image->type, (VkOffset3D){
return radv_sanitize_image_offset(image->vk.image_type,
(VkOffset3D){
.x = offset->x / block.width,
.y = offset->y / block.height,
.z = offset->z / block.depth,
@@ -110,14 +111,15 @@ blit_surf_for_image_level_layer(struct radv_image *image, VkImageLayout layout,
bool
radv_image_is_renderable(struct radv_device *device, struct radv_image *image)
{
if (image->vk_format == VK_FORMAT_R32G32B32_UINT ||
image->vk_format == VK_FORMAT_R32G32B32_SINT ||
image->vk_format == VK_FORMAT_R32G32B32_SFLOAT)
if (image->vk.format == VK_FORMAT_R32G32B32_UINT ||
image->vk.format == VK_FORMAT_R32G32B32_SINT ||
image->vk.format == VK_FORMAT_R32G32B32_SFLOAT)
return false;
if (device->physical_device->rad_info.gfx_level >= GFX9 && image->type == VK_IMAGE_TYPE_3D &&
vk_format_get_blocksizebits(image->vk_format) == 128 &&
vk_format_is_compressed(image->vk_format))
if (device->physical_device->rad_info.gfx_level >= GFX9 &&
image->vk.image_type == VK_IMAGE_TYPE_3D &&
vk_format_get_blocksizebits(image->vk.format) == 128 &&
vk_format_is_compressed(image->vk.format))
return false;
return true;
}
@@ -164,10 +166,10 @@ copy_buffer_to_image(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buf
.width = region->bufferRowLength ? region->bufferRowLength : region->imageExtent.width,
.height = region->bufferImageHeight ? region->bufferImageHeight : region->imageExtent.height,
};
const VkExtent3D buf_extent_el = meta_region_extent_el(image, image->type, &bufferExtent);
const VkExtent3D buf_extent_el = meta_region_extent_el(image, image->vk.image_type, &bufferExtent);
/* Start creating blit rect */
const VkExtent3D img_extent_el = meta_region_extent_el(image, image->type, &region->imageExtent);
const VkExtent3D img_extent_el = meta_region_extent_el(image, image->vk.image_type, &region->imageExtent);
struct radv_meta_blit2d_rect rect = {
.width = img_extent_el.width,
.height = img_extent_el.height,
@@ -205,7 +207,7 @@ copy_buffer_to_image(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buf
.pitch = buf_extent_el.width,
};
if (image->type == VK_IMAGE_TYPE_3D)
if (image->vk.image_type == VK_IMAGE_TYPE_3D)
img_bsurf.layer = img_offset_el.z;
/* Loop through each 3D or array slice */
unsigned num_slices_3d = img_extent_el.depth;
@@ -231,7 +233,7 @@ copy_buffer_to_image(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buf
*/
buf_bsurf.offset += buf_extent_el.width * buf_extent_el.height * buf_bsurf.bs;
img_bsurf.layer++;
if (image->type == VK_IMAGE_TYPE_3D)
if (image->vk.image_type == VK_IMAGE_TYPE_3D)
slice_3d++;
else
slice_array++;
@@ -258,7 +260,7 @@ radv_CmdCopyBufferToImage2(VkCommandBuffer commandBuffer,
}
if (cmd_buffer->device->physical_device->emulate_etc2 &&
vk_format_description(dst_image->vk_format)->layout == UTIL_FORMAT_LAYOUT_ETC) {
vk_format_description(dst_image->vk.format)->layout == UTIL_FORMAT_LAYOUT_ETC) {
cmd_buffer->state.flush_bits |=
RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
radv_src_access_flush(cmd_buffer, VK_ACCESS_TRANSFER_WRITE_BIT, dst_image) |
@@ -281,7 +283,7 @@ copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buf
if (cmd_buffer->qf == RADV_QUEUE_TRANSFER) {
/* RADV_QUEUE_TRANSFER should only be used for the prime blit */
assert(!region->imageOffset.x && !region->imageOffset.y && !region->imageOffset.z);
assert(image->type == VK_IMAGE_TYPE_2D);
assert(image->vk.image_type == VK_IMAGE_TYPE_2D);
assert(image->info.width == region->imageExtent.width);
assert(image->info.height == region->imageExtent.height);
ASSERTED bool res = radv_sdma_copy_image(cmd_buffer, image, buffer, region);
@@ -319,10 +321,10 @@ copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buf
.width = region->bufferRowLength ? region->bufferRowLength : region->imageExtent.width,
.height = region->bufferImageHeight ? region->bufferImageHeight : region->imageExtent.height,
};
const VkExtent3D buf_extent_el = meta_region_extent_el(image, image->type, &bufferExtent);
const VkExtent3D buf_extent_el = meta_region_extent_el(image, image->vk.image_type, &bufferExtent);
/* Start creating blit rect */
const VkExtent3D img_extent_el = meta_region_extent_el(image, image->type, &region->imageExtent);
const VkExtent3D img_extent_el = meta_region_extent_el(image, image->vk.image_type, &region->imageExtent);
struct radv_meta_blit2d_rect rect = {
.width = img_extent_el.width,
.height = img_extent_el.height,
@@ -360,7 +362,7 @@ copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buf
.pitch = buf_extent_el.width,
};
if (image->type == VK_IMAGE_TYPE_3D)
if (image->vk.image_type == VK_IMAGE_TYPE_3D)
img_info.layer = img_offset_el.z;
/* Loop through each 3D or array slice */
unsigned num_slices_3d = img_extent_el.depth;
@@ -377,7 +379,7 @@ copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buf
buf_info.offset += buf_extent_el.width * buf_extent_el.height * buf_info.bs;
img_info.layer++;
if (image->type == VK_IMAGE_TYPE_3D)
if (image->vk.image_type == VK_IMAGE_TYPE_3D)
slice_3d++;
else
slice_array++;
@@ -541,7 +543,7 @@ copy_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
* a 3D image.
*/
const VkExtent3D img_extent_el =
meta_region_extent_el(src_image, dst_image->type, &region->extent);
meta_region_extent_el(src_image, dst_image->vk.image_type, &region->extent);
/* Start creating blit rect */
struct radv_meta_blit2d_rect rect = {
@@ -549,10 +551,10 @@ copy_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
.height = img_extent_el.height,
};
if (src_image->type == VK_IMAGE_TYPE_3D)
if (src_image->vk.image_type == VK_IMAGE_TYPE_3D)
b_src.layer = src_offset_el.z;
if (dst_image->type == VK_IMAGE_TYPE_3D)
if (dst_image->vk.image_type == VK_IMAGE_TYPE_3D)
b_dst.layer = dst_offset_el.z;
/* Loop through each 3D or array slice */
@@ -581,7 +583,7 @@ copy_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
b_src.layer++;
b_dst.layer++;
if (dst_image->type == VK_IMAGE_TYPE_3D)
if (dst_image->vk.image_type == VK_IMAGE_TYPE_3D)
slice_3d++;
else
slice_array++;
@@ -631,7 +633,7 @@ radv_CmdCopyImage2(VkCommandBuffer commandBuffer, const VkCopyImageInfo2 *pCopyI
}
if (cmd_buffer->device->physical_device->emulate_etc2 &&
vk_format_description(dst_image->vk_format)->layout == UTIL_FORMAT_LAYOUT_ETC) {
vk_format_description(dst_image->vk.format)->layout == UTIL_FORMAT_LAYOUT_ETC) {
cmd_buffer->state.flush_bits |=
RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
radv_src_access_flush(cmd_buffer, VK_ACCESS_TRANSFER_WRITE_BIT, dst_image) |

2
src/amd/vulkan/radv_meta_copy_vrs_htile.c
View File

@@ -245,7 +245,7 @@ radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_i
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(vrs_image),
.viewType = VK_IMAGE_VIEW_TYPE_2D,
.format = vrs_image->vk_format,
.format = vrs_image->vk.format,
.subresourceRange = {.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
.baseMipLevel = 0,
.levelCount = 1,

6
src/amd/vulkan/radv_meta_dcc_retile.c
View File

@@ -186,7 +186,7 @@ radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image)
struct radv_device *device = cmd_buffer->device;
struct radv_buffer buffer;
assert(image->type == VK_IMAGE_TYPE_2D);
assert(image->vk.image_type == VK_IMAGE_TYPE_2D);
assert(image->info.array_size == 1 && image->info.levels == 1);
struct radv_cmd_state *state = &cmd_buffer->state;
@@ -258,8 +258,8 @@ radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image)
},
});
unsigned width = DIV_ROUND_UP(image->info.width, vk_format_get_blockwidth(image->vk_format));
unsigned height = DIV_ROUND_UP(image->info.height, vk_format_get_blockheight(image->vk_format));
unsigned width = DIV_ROUND_UP(image->info.width, vk_format_get_blockwidth(image->vk.format));
unsigned height = DIV_ROUND_UP(image->info.height, vk_format_get_blockheight(image->vk.format));
unsigned dcc_width = DIV_ROUND_UP(width, image->planes[0].surface.u.gfx9.color.dcc_block_width);
unsigned dcc_height =

8
src/amd/vulkan/radv_meta_decompress.c
View File

@@ -419,7 +419,7 @@ radv_process_depth_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_i
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(image),
.viewType = radv_meta_get_view_type(image),
.format = image->vk_format,
.format = image->vk.format,
.subresourceRange =
{
.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT,
@@ -486,7 +486,7 @@ radv_process_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image
*pipeline);
if (sample_locs) {
assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
assert(image->vk.create_flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
/* Set the sample locations specified during explicit or
* automatic layout transitions, otherwise the depth decompress
@@ -569,7 +569,7 @@ radv_expand_depth_stencil_compute(struct radv_cmd_buffer *cmd_buffer, struct rad
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(image),
.viewType = VK_IMAGE_VIEW_TYPE_2D,
.format = image->vk_format,
.format = image->vk.format,
.subresourceRange = {.aspectMask = subresourceRange->aspectMask,
.baseMipLevel = subresourceRange->baseMipLevel + l,
.levelCount = 1,
@@ -583,7 +583,7 @@ radv_expand_depth_stencil_compute(struct radv_cmd_buffer *cmd_buffer, struct rad
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(image),
.viewType = VK_IMAGE_VIEW_TYPE_2D,
.format = image->vk_format,
.format = image->vk.format,
.subresourceRange = {.aspectMask = subresourceRange->aspectMask,
.baseMipLevel = subresourceRange->baseMipLevel + l,
.levelCount = 1,

12
src/amd/vulkan/radv_meta_etc_decode.c
View File

@@ -705,7 +705,7 @@ decode_etc(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *src_iview
pipeline);
unsigned push_constants[5] = {
offset->x, offset->y, offset->z, src_iview->image->vk_format, src_iview->image->type,
offset->x, offset->y, offset->z, src_iview->image->vk.format, src_iview->image->vk.image_type,
};
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
@@ -728,12 +728,12 @@ radv_meta_decode_etc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *imag
cmd_buffer->state.predicating = false;
uint32_t base_slice = radv_meta_get_iview_layer(image, subresource, &offset);
uint32_t slice_count = image->type == VK_IMAGE_TYPE_3D ? extent.depth : subresource->layerCount;
uint32_t slice_count = image->vk.image_type == VK_IMAGE_TYPE_3D ? extent.depth : subresource->layerCount;
extent = radv_sanitize_image_extent(image->type, extent);
offset = radv_sanitize_image_offset(image->type, offset);
extent = radv_sanitize_image_extent(image->vk.image_type, extent);
offset = radv_sanitize_image_offset(image->vk.image_type, offset);
VkFormat load_format = vk_format_get_blocksize(image->vk_format) == 16
VkFormat load_format = vk_format_get_blocksize(image->vk.format) == 16
? VK_FORMAT_R32G32B32A32_UINT
: VK_FORMAT_R32G32_UINT;
struct radv_image_view src_iview;
@@ -756,7 +756,7 @@ radv_meta_decode_etc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *imag
0, NULL);
VkFormat store_format;
switch (image->vk_format) {
switch (image->vk.format) {
case VK_FORMAT_EAC_R11_UNORM_BLOCK:
store_format = VK_FORMAT_R16_UNORM;
break;

6
src/amd/vulkan/radv_meta_fast_clear.c
View File

@@ -496,7 +496,7 @@ radv_process_color_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_i
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(image),
.viewType = radv_meta_get_view_type(image),
.format = image->vk_format,
.format = image->vk.format,
.subresourceRange =
{
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
@@ -760,7 +760,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_imag
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(image),
.viewType = VK_IMAGE_VIEW_TYPE_2D,
.format = image->vk_format,
.format = image->vk.format,
.subresourceRange = {.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
.baseMipLevel = subresourceRange->baseMipLevel + l,
.levelCount = 1,
@@ -774,7 +774,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_imag
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(image),
.viewType = VK_IMAGE_VIEW_TYPE_2D,
.format = image->vk_format,
.format = image->vk.format,
.subresourceRange = {.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
.baseMipLevel = subresourceRange->baseMipLevel + l,
.levelCount = 1,

4
src/amd/vulkan/radv_meta_fmask_copy.c
View File

@@ -304,7 +304,7 @@ radv_fmask_copy(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(src->image),
.viewType = radv_meta_get_view_type(src->image),
.format = vk_format_no_srgb(src->image->vk_format),
.format = vk_format_no_srgb(src->image->vk.format),
.subresourceRange =
{
.aspectMask = src->aspect_mask,
@@ -321,7 +321,7 @@ radv_fmask_copy(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(dst->image),
.viewType = radv_meta_get_view_type(dst->image),
.format = vk_format_no_srgb(dst->image->vk_format),
.format = vk_format_no_srgb(dst->image->vk.format),
.subresourceRange =
{
.aspectMask = dst->aspect_mask,

2
src/amd/vulkan/radv_meta_fmask_expand.c
View File

@@ -114,7 +114,7 @@ radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer, struct radv_
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(image),
.viewType = radv_meta_get_view_type(image),
.format = vk_format_no_srgb(image->vk_format),
.format = vk_format_no_srgb(image->vk.format),
.subresourceRange =
{
.aspectMask = subresourceRange->aspectMask,

18
src/amd/vulkan/radv_meta_resolve.c
View File

@@ -369,7 +369,7 @@ radv_meta_resolve_hardware_image(struct radv_cmd_buffer *cmd_buffer, struct radv
assert(src_image->info.samples > 1);
assert(dst_image->info.samples == 1);
unsigned fs_key = radv_format_meta_fs_key(device, dst_image->vk_format);
unsigned fs_key = radv_format_meta_fs_key(device, dst_image->vk.format);
/* From the Vulkan 1.0 spec:
*
@@ -402,9 +402,9 @@ radv_meta_resolve_hardware_image(struct radv_cmd_buffer *cmd_buffer, struct radv
* height and depth. 1D images use only x and width. 2D images use x, y,
* width and height. 3D images use x, y, z, width, height and depth.
*/
const struct VkExtent3D extent = radv_sanitize_image_extent(src_image->type, region->extent);
const struct VkExtent3D extent = radv_sanitize_image_extent(src_image->vk.image_type, region->extent);
const struct VkOffset3D dstOffset =
radv_sanitize_image_offset(dst_image->type, region->dstOffset);
radv_sanitize_image_offset(dst_image->vk.image_type, region->dstOffset);
uint32_t queue_mask = radv_image_queue_family_mask(dst_image, cmd_buffer->qf,
cmd_buffer->qf);
@@ -436,7 +436,7 @@ radv_meta_resolve_hardware_image(struct radv_cmd_buffer *cmd_buffer, struct radv
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(src_image),
.viewType = radv_meta_get_view_type(src_image),
.format = src_image->vk_format,
.format = src_image->vk.format,
.subresourceRange =
{
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
@@ -454,7 +454,7 @@ radv_meta_resolve_hardware_image(struct radv_cmd_buffer *cmd_buffer, struct radv
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(dst_image),
.viewType = radv_meta_get_view_type(dst_image),
.format = dst_image->vk_format,
.format = dst_image->vk.format,
.subresourceRange =
{
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
@@ -531,8 +531,8 @@ resolve_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
dst_image_layout, region);
break;
case RESOLVE_COMPUTE:
radv_meta_resolve_compute_image(cmd_buffer, src_image, src_image->vk_format, src_image_layout,
dst_image, dst_image->vk_format, dst_image_layout, region);
radv_meta_resolve_compute_image(cmd_buffer, src_image, src_image->vk.format, src_image_layout,
dst_image, dst_image->vk.format, dst_image_layout, region);
break;
default:
assert(!"Invalid resolve method selected");
@@ -568,7 +568,7 @@ radv_CmdResolveImage2(VkCommandBuffer commandBuffer,
for (uint32_t r = 0; r < pResolveImageInfo->regionCount; r++) {
const VkImageResolve2 *region = &pResolveImageInfo->pRegions[r];
radv_pick_resolve_method_images(cmd_buffer->device, src_image, src_image->vk_format, dst_image,
radv_pick_resolve_method_images(cmd_buffer->device, src_image, src_image->vk.format, dst_image,
region->dstSubresource.mipLevel, dst_image_layout, false,
cmd_buffer, &resolve_method);
@@ -836,7 +836,7 @@ radv_decompress_resolve_src(struct radv_cmd_buffer *cmd_buffer, struct radv_imag
}
};
if (src_image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT) {
if (src_image->vk.create_flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT) {
/* If the depth/stencil image uses different sample
* locations, we need them during HTILE decompressions.
*/

6
src/amd/vulkan/radv_meta_resolve_cs.c
View File

@@ -700,11 +700,11 @@ radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer, struct radv_
const uint32_t dest_base_layer =
radv_meta_get_iview_layer(dest_image, &region->dstSubresource, &region->dstOffset);
const struct VkExtent3D extent = radv_sanitize_image_extent(src_image->type, region->extent);
const struct VkExtent3D extent = radv_sanitize_image_extent(src_image->vk.image_type, region->extent);
const struct VkOffset3D srcOffset =
radv_sanitize_image_offset(src_image->type, region->srcOffset);
radv_sanitize_image_offset(src_image->vk.image_type, region->srcOffset);
const struct VkOffset3D dstOffset =
radv_sanitize_image_offset(dest_image->type, region->dstOffset);
radv_sanitize_image_offset(dest_image->vk.image_type, region->dstOffset);
for (uint32_t layer = 0; layer < region->srcSubresource.layerCount; ++layer) {

10
src/amd/vulkan/radv_meta_resolve_fs.c
View File

@@ -815,11 +815,11 @@ radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer, struct radv
const uint32_t dest_base_layer =
radv_meta_get_iview_layer(dest_image, &region->dstSubresource, &region->dstOffset);
const struct VkExtent3D extent = radv_sanitize_image_extent(src_image->type, region->extent);
const struct VkExtent3D extent = radv_sanitize_image_extent(src_image->vk.image_type, region->extent);
const struct VkOffset3D srcOffset =
radv_sanitize_image_offset(src_image->type, region->srcOffset);
radv_sanitize_image_offset(src_image->vk.image_type, region->srcOffset);
const struct VkOffset3D dstOffset =
radv_sanitize_image_offset(dest_image->type, region->dstOffset);
radv_sanitize_image_offset(dest_image->vk.image_type, region->dstOffset);
for (uint32_t layer = 0; layer < region->srcSubresource.layerCount; ++layer) {
@@ -829,7 +829,7 @@ radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer, struct radv
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(src_image),
.viewType = radv_meta_get_view_type(src_image),
.format = src_image->vk_format,
.format = src_image->vk.format,
.subresourceRange =
{
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
@@ -847,7 +847,7 @@ radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer, struct radv
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(dest_image),
.viewType = radv_meta_get_view_type(dest_image),
.format = dest_image->vk_format,
.format = dest_image->vk.format,
.subresourceRange =
{
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,

21
src/amd/vulkan/radv_private.h
View File

@@ -2113,16 +2113,9 @@ struct radv_image_plane {
};
struct radv_image {
struct vk_object_base base;
VkImageType type;
/* The original VkFormat provided by the client. This may not match any
* of the actual surface formats.
*/
VkFormat vk_format;
VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
struct vk_image vk;
struct ac_surf_info info;
VkImageTiling tiling; /** VkImageCreateInfo::tiling */
VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
VkDeviceSize size;
uint32_t alignment;
@@ -2252,7 +2245,7 @@ radv_image_has_vrs_htile(const struct radv_device *device, const struct radv_ima
{
/* Any depth buffer can potentially use VRS. */
return device->attachment_vrs_enabled && radv_image_has_htile(image) &&
(image->usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT);
(image->vk.usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT);
}
/**
@@ -2282,12 +2275,12 @@ static inline bool
radv_image_tile_stencil_disabled(const struct radv_device *device, const struct radv_image *image)
{
if (device->physical_device->rad_info.gfx_level >= GFX9) {
return !vk_format_has_stencil(image->vk_format) && !radv_image_has_vrs_htile(device, image);
return !vk_format_has_stencil(image->vk.format) && !radv_image_has_vrs_htile(device, image);
} else {
/* Due to a hw bug, TILE_STENCIL_DISABLE must be set to 0 for
* the TC-compat ZRANGE issue even if no stencil is used.
*/
return !vk_format_has_stencil(image->vk_format) && !radv_image_is_tc_compat_htile(image);
return !vk_format_has_stencil(image->vk.format) && !radv_image_is_tc_compat_htile(image);
}
}
@@ -2391,7 +2384,7 @@ radv_image_get_iterate256(struct radv_device *device, struct radv_image *image)
{
/* ITERATE_256 is required for depth or stencil MSAA images that are TC-compatible HTILE. */
return device->physical_device->rad_info.gfx_level >= GFX10 &&
(image->usage &
(image->vk.usage &
(VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT | VK_IMAGE_USAGE_TRANSFER_DST_BIT)) &&
radv_image_is_tc_compat_htile(image) && image->info.samples > 1;
}
@@ -3025,7 +3018,7 @@ VK_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, base,
VK_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, base, VkDeviceMemory,
VK_OBJECT_TYPE_DEVICE_MEMORY)
VK_DEFINE_NONDISP_HANDLE_CASTS(radv_event, base, VkEvent, VK_OBJECT_TYPE_EVENT)
VK_DEFINE_NONDISP_HANDLE_CASTS(radv_image, base, VkImage, VK_OBJECT_TYPE_IMAGE)
VK_DEFINE_NONDISP_HANDLE_CASTS(radv_image, vk.base, VkImage, VK_OBJECT_TYPE_IMAGE)
VK_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, base, VkImageView,
VK_OBJECT_TYPE_IMAGE_VIEW);
VK_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, base, VkPipelineCache,

4
src/amd/vulkan/radv_sdma_copy_image.c
View File

@@ -163,14 +163,14 @@ radv_sdma_v4_v5_copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct
unsigned hw_fmt, hw_type;
uint64_t md_address = tiled_address + image->planes[0].surface.meta_offset;
radv_translate_format_to_hw(&device->physical_device->rad_info, image->vk_format, &hw_fmt,
radv_translate_format_to_hw(&device->physical_device->rad_info, image->vk.format, &hw_fmt,
&hw_type);
/* Add metadata */
radeon_emit(cmd_buffer->cs, (uint32_t)md_address);
radeon_emit(cmd_buffer->cs, (uint32_t)(md_address >> 32));
radeon_emit(cmd_buffer->cs,
hw_fmt | vi_alpha_is_on_msb(device, image->vk_format) << 8 | hw_type << 9 |
hw_fmt | vi_alpha_is_on_msb(device, image->vk.format) << 8 | hw_type << 9 |
image->planes[0].surface.u.gfx9.color.dcc.max_compressed_block_size << 24 |
V_028C78_MAX_BLOCK_SIZE_256B << 26 | tmz << 29 |
image->planes[0].surface.u.gfx9.color.dcc.pipe_aligned << 31);