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i965/gen7: Use the updated interface for SO write pointer resetting.

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The new kernel patch I submitted makes the interface opt-in, so all
batchbuffers aren't preceded by the 4 MI_LOAD_REGISTER_IMMs.  This
requires the updated i915_drm.h present in libdrm 2.4.30.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Eric Anholt
2011-12-29 18:12:48 -08:00
parent e60daf7e25
commit c4089d444a
4 changed files with 13 additions and 5 deletions
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2
configure.ac
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@@ -25,7 +25,7 @@ USER_CXXFLAGS="$CXXFLAGS"
dnl Versions for external dependencies dnl Versions for external dependencies
LIBDRM_REQUIRED=2.4.24 LIBDRM_REQUIRED=2.4.24
LIBDRM_RADEON_REQUIRED=2.4.24 LIBDRM_RADEON_REQUIRED=2.4.24
LIBDRM_INTEL_REQUIRED=2.4.27 LIBDRM_INTEL_REQUIRED=2.4.30
LIBDRM_NOUVEAU_REQUIRED=0.6 LIBDRM_NOUVEAU_REQUIRED=0.6
DRI2PROTO_REQUIRED=2.6 DRI2PROTO_REQUIRED=2.6
GLPROTO_REQUIRED=1.4.14 GLPROTO_REQUIRED=1.4.14

2
src/mesa/drivers/dri/i965/gen7_sol_state.c
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@@ -240,6 +240,8 @@ upload_sol_state(struct brw_context *brw)
if (active) { if (active) {
upload_3dstate_so_buffers(brw); upload_3dstate_so_buffers(brw);
upload_3dstate_so_decl_list(brw, &vue_map); upload_3dstate_so_decl_list(brw, &vue_map);
intel->batch.needs_sol_reset = true;
} }
/* Finally, set up the SOL stage. This command must always follow updates to /* Finally, set up the SOL stage. This command must always follow updates to

13
src/mesa/drivers/dri/intel/intel_batchbuffer.c
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@@ -85,6 +85,7 @@ intel_batchbuffer_reset(struct intel_context *intel)
intel->batch.reserved_space = BATCH_RESERVED; intel->batch.reserved_space = BATCH_RESERVED;
intel->batch.state_batch_offset = intel->batch.bo->size; intel->batch.state_batch_offset = intel->batch.bo->size;
intel->batch.used = 0; intel->batch.used = 0;
intel->batch.needs_sol_reset = false;
} }
void void
@@ -135,16 +136,20 @@ do_flush_locked(struct intel_context *intel)
} }
if (!intel->intelScreen->no_hw) { if (!intel->intelScreen->no_hw) {
int ring; int flags;
if (intel->gen < 6 || !batch->is_blit) { if (intel->gen < 6 || !batch->is_blit) {
ring = I915_EXEC_RENDER; flags = I915_EXEC_RENDER;
} else { } else {
ring = I915_EXEC_BLT; flags = I915_EXEC_BLT;
} }
if (batch->needs_sol_reset)
flags |= I915_EXEC_GEN7_SOL_RESET;
if (ret == 0) if (ret == 0)
ret = drm_intel_bo_mrb_exec(batch->bo, 4*batch->used, NULL, 0, 0, ring); ret = drm_intel_bo_mrb_exec(batch->bo, 4*batch->used, NULL, 0, 0,
flags);
} }
if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) { if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {

1
src/mesa/drivers/dri/intel/intel_context.h
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@@ -233,6 +233,7 @@ struct intel_context
uint32_t state_batch_offset; uint32_t state_batch_offset;
bool is_blit; bool is_blit;
bool needs_sol_reset;
struct { struct {
uint16_t used; uint16_t used;