i965/gen7: Use the updated interface for SO write pointer resetting.
The new kernel patch I submitted makes the interface opt-in, so all batchbuffers aren't preceded by the 4 MI_LOAD_REGISTER_IMMs. This requires the updated i915_drm.h present in libdrm 2.4.30. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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@@ -25,7 +25,7 @@ USER_CXXFLAGS="$CXXFLAGS"
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dnl Versions for external dependencies
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LIBDRM_REQUIRED=2.4.24
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LIBDRM_RADEON_REQUIRED=2.4.24
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LIBDRM_INTEL_REQUIRED=2.4.27
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LIBDRM_INTEL_REQUIRED=2.4.30
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LIBDRM_NOUVEAU_REQUIRED=0.6
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DRI2PROTO_REQUIRED=2.6
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GLPROTO_REQUIRED=1.4.14
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@@ -240,6 +240,8 @@ upload_sol_state(struct brw_context *brw)
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if (active) {
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upload_3dstate_so_buffers(brw);
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upload_3dstate_so_decl_list(brw, &vue_map);
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intel->batch.needs_sol_reset = true;
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}
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/* Finally, set up the SOL stage. This command must always follow updates to
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@@ -85,6 +85,7 @@ intel_batchbuffer_reset(struct intel_context *intel)
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intel->batch.reserved_space = BATCH_RESERVED;
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intel->batch.state_batch_offset = intel->batch.bo->size;
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intel->batch.used = 0;
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intel->batch.needs_sol_reset = false;
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}
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void
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@@ -135,16 +136,20 @@ do_flush_locked(struct intel_context *intel)
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}
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if (!intel->intelScreen->no_hw) {
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int ring;
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int flags;
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if (intel->gen < 6 || !batch->is_blit) {
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ring = I915_EXEC_RENDER;
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flags = I915_EXEC_RENDER;
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} else {
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ring = I915_EXEC_BLT;
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flags = I915_EXEC_BLT;
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}
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if (batch->needs_sol_reset)
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flags |= I915_EXEC_GEN7_SOL_RESET;
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if (ret == 0)
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ret = drm_intel_bo_mrb_exec(batch->bo, 4*batch->used, NULL, 0, 0, ring);
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ret = drm_intel_bo_mrb_exec(batch->bo, 4*batch->used, NULL, 0, 0,
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flags);
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}
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if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
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@@ -233,6 +233,7 @@ struct intel_context
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uint32_t state_batch_offset;
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bool is_blit;
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bool needs_sol_reset;
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struct {
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uint16_t used;
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