radv: add RADV_DCC_CLEAR_SINGLE

When DCC is cleared with that code, the hardware expects the clear
color value to be stored at the beginning of each 256B block in
the image.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10518>

src/amd/vulkan/radv_meta_clear.c

@@ -1421,6 +1421,7 @@ enum {
    RADV_DCC_CLEAR_1110 = 0x80808080U,
    RADV_DCC_CLEAR_1111 = 0xC0C0C0C0U,
    RADV_DCC_CLEAR_REG = 0x20202020U,
+   RADV_DCC_CLEAR_SINGLE = 0x10101010U,
 };
 
 static void