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intel/compiler: Inline TUE map computation into TUE Input lowering

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Refactor since the TUE compute function is simpler now and the
comments make sense being near the lowering.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15022>
This commit is contained in:
Caio Oliveira
2022-02-14 16:40:54 -08:00
committed by Marge Bot
parent c36ae42e4c
commit c32d386ce2
1 changed files with 13 additions and 20 deletions
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33
src/intel/compiler/brw_mesh.cpp
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@@ -91,23 +91,7 @@ shared_type_info(const struct glsl_type *type, unsigned *size, unsigned *align)
}
static void
brw_nir_lower_tue_outputs(nir_shader *nir, const brw_tue_map *map)
{
nir_foreach_shader_out_variable(var, nir) {
assert(var->data.location == VARYING_SLOT_TASK_COUNT);
/* First word in TUE header. */
var->data.driver_location = 0;
}
nir_lower_io(nir, nir_var_shader_out, type_size_scalar_dwords,
nir_lower_io_lower_64bit_to_32);
nir_lower_explicit_io(nir, nir_var_mem_task_payload,
nir_address_format_32bit_offset);
}
static void
brw_compute_tue_map(struct nir_shader *nir, struct brw_tue_map *map)
brw_nir_lower_tue_outputs(nir_shader *nir, brw_tue_map *map)
{
memset(map, 0, sizeof(*map));
@@ -117,8 +101,16 @@ brw_compute_tue_map(struct nir_shader *nir, struct brw_tue_map *map)
*
* - Words 1-3 used for "Dispatch Dimensions" feature, to allow mapping a
* 3D dispatch into the 1D dispatch supported by HW. Currently not used.
*
* From bspec: "It is suggested that SW reserve the 16 bytes following the
*/
nir_foreach_shader_out_variable(var, nir) {
assert(var->data.location == VARYING_SLOT_TASK_COUNT);
var->data.driver_location = 0;
}
nir_lower_io(nir, nir_var_shader_out, type_size_scalar_dwords,
nir_lower_io_lower_64bit_to_32);
/* From bspec: "It is suggested that SW reserve the 16 bytes following the
* TUE Header, and therefore start the SW-defined data structure at 32B
* alignment. This allows the TUE Header to always be written as 32 bytes
* with 32B alignment, the most optimal write performance case."
@@ -131,6 +123,8 @@ brw_compute_tue_map(struct nir_shader *nir, struct brw_tue_map *map)
nir->info.task_payload_size = map->per_task_data_start_dw * 4;
nir_lower_vars_to_explicit_types(nir, nir_var_mem_task_payload,
shared_type_info);
nir_lower_explicit_io(nir, nir_var_mem_task_payload,
nir_address_format_32bit_offset);
map->size_dw = ALIGN(DIV_ROUND_UP(nir->info.task_payload_size, 4), 8);
}
@@ -207,7 +201,6 @@ brw_compile_task(const struct brw_compiler *compiler,
prog_data->uses_drawid =
BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID);
brw_compute_tue_map(nir, &prog_data->map);
NIR_PASS_V(nir, brw_nir_lower_tue_outputs, &prog_data->map);
NIR_PASS_V(nir, brw_nir_adjust_task_payload_offsets);