i915: Attempt to schedule buffer swap on target vertical blank when possible.
This has some advantages over the traditional way of first waiting for the target vertical blank and then emitting the buffer swap, e.g. * glXSwapBuffers returns immediately, only the next time the driver needs the hardware lock will it block until the target vertical blank. This should allow applications that don't intermix rendering and other processing to start processing for the next frame right away. * It's less likely to produce tearing.
This commit is contained in:
Michel Dänzer
@@ -368,6 +368,7 @@ void intelCopyBuffer( const __DRIdrawablePrivate *dPriv,
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const drm_clip_rect_t *rect)
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const drm_clip_rect_t *rect)
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{
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{
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intelContextPtr intel;
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intelContextPtr intel;
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const intelScreenPrivate *intelScreen;
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GLboolean missed_target;
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GLboolean missed_target;
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int64_t ust;
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int64_t ust;
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@@ -382,97 +383,130 @@ void intelCopyBuffer( const __DRIdrawablePrivate *dPriv,
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intelFlush( &intel->ctx );
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intelFlush( &intel->ctx );
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intelWaitForFrameCompletion( intel );
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intelScreen = intel->intelScreen;
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LOCK_HARDWARE( intel );
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if (!rect)
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if (!rect && !intel->swap_scheduled && intelScreen->drmMinor >= 6 &&
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{
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!(intel->vblank_flags & VBLANK_FLAG_NO_IRQ) &&
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UNLOCK_HARDWARE( intel );
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intelScreen->current_rotation == 0) {
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driWaitForVBlank( dPriv, &intel->vbl_seq, intel->vblank_flags, & missed_target );
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unsigned int interval = driGetVBlankInterval(dPriv, intel->vblank_flags);
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LOCK_HARDWARE( intel );
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unsigned int target;
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}
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drm_i915_vblank_swap_t swap;
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{
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const intelScreenPrivate *intelScreen = intel->intelScreen;
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const __DRIdrawablePrivate *dPriv = intel->driDrawable;
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const int nbox = dPriv->numClipRects;
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const drm_clip_rect_t *pbox = dPriv->pClipRects;
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drm_clip_rect_t box;
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const int cpp = intelScreen->cpp;
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const int pitch = intelScreen->front.pitch; /* in bytes */
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int i;
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GLuint CMD, BR13;
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BATCH_LOCALS;
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switch(cpp) {
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swap.drawable = dPriv->hHWDrawable;
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case 2:
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swap.seqtype = DRM_VBLANK_ABSOLUTE;
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BR13 = (pitch) | (0xCC << 16) | (1<<24);
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target = swap.sequence = intel->vbl_seq + interval;
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CMD = XY_SRC_COPY_BLT_CMD;
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break;
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if (intel->vblank_flags & VBLANK_FLAG_SYNC) {
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case 4:
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swap.seqtype |= DRM_VBLANK_NEXTONMISS;
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BR13 = (pitch) | (0xCC << 16) | (1<<24) | (1<<25);
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} else if (interval == 0) {
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CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
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goto noschedule;
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XY_SRC_COPY_BLT_WRITE_RGB);
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break;
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default:
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BR13 = (pitch) | (0xCC << 16) | (1<<24);
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CMD = XY_SRC_COPY_BLT_CMD;
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break;
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}
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}
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if (0)
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intel_draw_performance_boxes( intel );
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for (i = 0 ; i < nbox; i++, pbox++)
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if (!drmCommandWriteRead(intel->driFd, DRM_I915_VBLANK_SWAP, &swap,
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sizeof(swap))) {
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intel->swap_scheduled = 1;
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intel->vbl_seq = swap.sequence;
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swap.sequence -= target;
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missed_target = swap.sequence > 0 && swap.sequence <= (1 << 23);
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}
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} else {
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intel->swap_scheduled = 0;
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}
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noschedule:
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if (!intel->swap_scheduled) {
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intelWaitForFrameCompletion( intel );
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LOCK_HARDWARE( intel );
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if (!rect)
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{
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{
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if (pbox->x1 > pbox->x2 ||
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UNLOCK_HARDWARE( intel );
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pbox->y1 > pbox->y2 ||
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driWaitForVBlank( dPriv, &intel->vbl_seq, intel->vblank_flags, & missed_target );
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pbox->x2 > intelScreen->width ||
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LOCK_HARDWARE( intel );
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pbox->y2 > intelScreen->height) {
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_mesa_warning(&intel->ctx, "Bad cliprect in intelCopyBuffer()");
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continue;
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}
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box = *pbox;
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if (rect)
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{
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if (rect->x1 > box.x1)
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box.x1 = rect->x1;
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if (rect->y1 > box.y1)
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box.y1 = rect->y1;
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if (rect->x2 < box.x2)
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box.x2 = rect->x2;
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if (rect->y2 < box.y2)
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box.y2 = rect->y2;
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if (box.x1 > box.x2 || box.y1 > box.y2)
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continue;
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}
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BEGIN_BATCH( 8);
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OUT_BATCH( CMD );
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OUT_BATCH( BR13 );
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OUT_BATCH( (box.y1 << 16) | box.x1 );
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OUT_BATCH( (box.y2 << 16) | box.x2 );
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if (intel->sarea->pf_current_page == 0)
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OUT_BATCH( intelScreen->front.offset );
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else
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OUT_BATCH( intelScreen->back.offset );
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OUT_BATCH( (box.y1 << 16) | box.x1 );
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OUT_BATCH( BR13 & 0xffff );
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if (intel->sarea->pf_current_page == 0)
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OUT_BATCH( intelScreen->back.offset );
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else
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OUT_BATCH( intelScreen->front.offset );
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ADVANCE_BATCH();
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}
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}
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{
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const intelScreenPrivate *intelScreen = intel->intelScreen;
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const __DRIdrawablePrivate *dPriv = intel->driDrawable;
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const int nbox = dPriv->numClipRects;
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const drm_clip_rect_t *pbox = dPriv->pClipRects;
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drm_clip_rect_t box;
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const int cpp = intelScreen->cpp;
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const int pitch = intelScreen->front.pitch; /* in bytes */
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int i;
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GLuint CMD, BR13;
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BATCH_LOCALS;
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switch(cpp) {
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case 2:
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BR13 = (pitch) | (0xCC << 16) | (1<<24);
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CMD = XY_SRC_COPY_BLT_CMD;
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break;
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case 4:
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BR13 = (pitch) | (0xCC << 16) | (1<<24) | (1<<25);
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CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
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XY_SRC_COPY_BLT_WRITE_RGB);
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break;
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default:
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BR13 = (pitch) | (0xCC << 16) | (1<<24);
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CMD = XY_SRC_COPY_BLT_CMD;
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break;
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}
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if (0)
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intel_draw_performance_boxes( intel );
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for (i = 0 ; i < nbox; i++, pbox++)
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{
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if (pbox->x1 > pbox->x2 ||
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pbox->y1 > pbox->y2 ||
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pbox->x2 > intelScreen->width ||
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pbox->y2 > intelScreen->height) {
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_mesa_warning(&intel->ctx, "Bad cliprect in intelCopyBuffer()");
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continue;
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}
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box = *pbox;
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if (rect)
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{
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if (rect->x1 > box.x1)
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box.x1 = rect->x1;
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if (rect->y1 > box.y1)
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box.y1 = rect->y1;
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if (rect->x2 < box.x2)
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box.x2 = rect->x2;
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if (rect->y2 < box.y2)
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box.y2 = rect->y2;
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if (box.x1 > box.x2 || box.y1 > box.y2)
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continue;
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}
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BEGIN_BATCH( 8);
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OUT_BATCH( CMD );
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OUT_BATCH( BR13 );
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OUT_BATCH( (box.y1 << 16) | box.x1 );
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OUT_BATCH( (box.y2 << 16) | box.x2 );
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if (intel->sarea->pf_current_page == 0)
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OUT_BATCH( intelScreen->front.offset );
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else
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OUT_BATCH( intelScreen->back.offset );
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OUT_BATCH( (box.y1 << 16) | box.x1 );
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OUT_BATCH( BR13 & 0xffff );
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if (intel->sarea->pf_current_page == 0)
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OUT_BATCH( intelScreen->back.offset );
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else
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OUT_BATCH( intelScreen->front.offset );
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ADVANCE_BATCH();
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}
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}
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intelFlushBatchLocked( intel, GL_TRUE, GL_TRUE, GL_TRUE );
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UNLOCK_HARDWARE( intel );
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}
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}
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intelFlushBatchLocked( intel, GL_TRUE, GL_TRUE, GL_TRUE );
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UNLOCK_HARDWARE( intel );
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if (!rect)
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if (!rect)
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{
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{
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@@ -261,6 +261,8 @@ struct intel_context
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GLuint swap_count;
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GLuint swap_count;
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GLuint swap_missed_count;
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GLuint swap_missed_count;
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GLuint swap_scheduled;
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};
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};
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@@ -321,6 +323,13 @@ do { \
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char __ret=0; \
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char __ret=0; \
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DEBUG_CHECK_LOCK(); \
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DEBUG_CHECK_LOCK(); \
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assert(!(intel)->locked); \
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assert(!(intel)->locked); \
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if ((intel)->swap_scheduled) { \
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drmVBlank vbl; \
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vbl.request.type = DRM_VBLANK_ABSOLUTE; \
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vbl.request.sequence = (intel)->vbl_seq; \
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drmWaitVBlank((intel)->driFd, &vbl); \
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(intel)->swap_scheduled = 0; \
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} \
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DRM_CAS((intel)->driHwLock, (intel)->hHWContext, \
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DRM_CAS((intel)->driHwLock, (intel)->hHWContext, \
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(DRM_LOCK_HELD|(intel)->hHWContext), __ret); \
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(DRM_LOCK_HELD|(intel)->hHWContext), __ret); \
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if (__ret) \
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if (__ret) \
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