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gallium/radeon: align alignments for better buffer reuse

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It's for the buffer cache.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
2016-05-08 13:40:40 +02:00
parent 544967faf5
commit c2377b394b
2 changed files with 2 additions and 0 deletions
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1
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
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@@ -470,6 +470,7 @@ amdgpu_bo_create(struct radeon_winsys *rws,
* like constant/uniform buffers, can benefit from better and more reuse.
*/
size = align64(size, ws->info.gart_page_size);
alignment = align(alignment, ws->info.gart_page_size);
/* Only set one usage bit each for domains and flags, or the cache manager
* might consider different sets of domains / flags compatible

1
src/gallium/winsys/radeon/drm/radeon_drm_bo.c
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@@ -732,6 +732,7 @@ radeon_winsys_bo_create(struct radeon_winsys *rws,
* like constant/uniform buffers, can benefit from better and more reuse.
*/
size = align(size, ws->info.gart_page_size);
alignment = align(alignment, ws->info.gart_page_size);
/* Only set one usage bit each for domains and flags, or the cache manager
* might consider different sets of domains / flags compatible