diff --git a/src/amd/common/ac_nir.h b/src/amd/common/ac_nir.h
index 1df91f42fe4..0be2ed50900 100644
--- a/src/amd/common/ac_nir.h
+++ b/src/amd/common/ac_nir.h
@@ -194,7 +194,7 @@ void
 ac_nir_lower_ngg_gs(nir_shader *shader, const ac_nir_lower_ngg_options *options);
 
 void
-ac_nir_lower_ngg_ms(nir_shader *shader,
+ac_nir_lower_ngg_mesh(nir_shader *shader,
                     enum amd_gfx_level gfx_level,
                     uint32_t clipdist_enable_mask,
                     const uint8_t *vs_output_param_offset,
diff --git a/src/amd/common/ac_nir_lower_ngg.c b/src/amd/common/ac_nir_lower_ngg.c
index 881037a9b6f..6ac41bd8c92 100644
--- a/src/amd/common/ac_nir_lower_ngg.c
+++ b/src/amd/common/ac_nir_lower_ngg.c
@@ -5020,7 +5020,7 @@ ms_calculate_output_layout(enum amd_gfx_level gfx_level, unsigned api_shared_siz
 }
 
 void
-ac_nir_lower_ngg_ms(nir_shader *shader,
+ac_nir_lower_ngg_mesh(nir_shader *shader,
                     enum amd_gfx_level gfx_level,
                     uint32_t clipdist_enable_mask,
                     const uint8_t *vs_output_param_offset,
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index f7436d05e40..8d3d28af8f3 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -803,7 +803,7 @@ radv_lower_ngg(struct radv_device *device, struct radv_shader_stage *ngg_stage,
       unsigned hw_workgroup_size = ALIGN(info->workgroup_size, info->wave_size);
 
       bool scratch_ring = false;
-      NIR_PASS_V(nir, ac_nir_lower_ngg_ms, options.gfx_level, options.clip_cull_dist_mask,
+      NIR_PASS_V(nir, ac_nir_lower_ngg_mesh, options.gfx_level, options.clip_cull_dist_mask,
                  options.vs_output_param_offset, options.has_param_exports, &scratch_ring, info->wave_size,
                  hw_workgroup_size, gfx_state->has_multiview_view_index, info->ms.has_query, pdev->mesh_fast_launch_2);
       ngg_stage->info.ms.needs_ms_scratch_ring = scratch_ring;