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radv: rename gfx9_gs_info to radv_legacy_gs_info

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This was misleading because it's also needed on GFX6-8.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22134>
This commit is contained in:
Samuel Pitoiset
2023-03-27 13:44:45 +02:00
committed by Marge Bot
parent bc6f95c53e
commit c1c8aa49c8
4 changed files with 12 additions and 11 deletions
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2
src/amd/vulkan/radv_cmd_buffer.c
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@@ -5219,7 +5219,7 @@ gfx10_emit_ge_cntl(struct radv_cmd_buffer *cmd_buffer)
break_wave_at_eoi = true; break_wave_at_eoi = true;
} }
} else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) { } else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
const struct gfx9_gs_info *gs_state = const struct radv_legacy_gs_info *gs_state =
&pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info; &pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(gs_state->vgt_gs_onchip_cntl); primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(gs_state->vgt_gs_onchip_cntl);
} else { } else {

9
src/amd/vulkan/radv_pipeline.c
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@@ -1412,8 +1412,9 @@ gfx10_emit_ge_pc_alloc(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level,
} }
static void static void
radv_pipeline_init_gs_ring_state(const struct radv_device *device, radv_pipeline_init_legacy_gs_ring_info(const struct radv_device *device,
struct radv_graphics_pipeline *pipeline, const struct gfx9_gs_info *gs) struct radv_graphics_pipeline *pipeline,
const struct radv_legacy_gs_info *gs)
{ {
const struct radv_physical_device *pdevice = device->physical_device; const struct radv_physical_device *pdevice = device->physical_device;
unsigned num_se = pdevice->rad_info.max_se; unsigned num_se = pdevice->rad_info.max_se;
@@ -4036,7 +4037,7 @@ radv_pipeline_emit_hw_gs(const struct radv_device *device, struct radeon_cmdbuf
const struct radv_shader *gs) const struct radv_shader *gs)
{ {
const struct radv_physical_device *pdevice = device->physical_device; const struct radv_physical_device *pdevice = device->physical_device;
const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info; const struct radv_legacy_gs_info *gs_state = &gs->info.gs_ring_info;
unsigned gs_max_out_vertices; unsigned gs_max_out_vertices;
const uint8_t *num_components; const uint8_t *num_components;
uint8_t max_stream; uint8_t max_stream;
@@ -4967,7 +4968,7 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) && !radv_pipeline_has_ngg(pipeline)) { if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) && !radv_pipeline_has_ngg(pipeline)) {
struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY]; struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY];
radv_pipeline_init_gs_ring_state(device, pipeline, &gs->info.gs_ring_info); radv_pipeline_init_legacy_gs_ring_info(device, pipeline, &gs->info.gs_ring_info);
} }
if (!radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH)) if (!radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH))

4
src/amd/vulkan/radv_shader.h
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@@ -220,7 +220,7 @@ struct radv_vs_output_info {
unsigned pos_exports; unsigned pos_exports;
}; };
struct gfx9_gs_info { struct radv_legacy_gs_info {
uint32_t vgt_gs_onchip_cntl; uint32_t vgt_gs_onchip_cntl;
uint32_t vgt_gs_max_prims_per_subgroup; uint32_t vgt_gs_max_prims_per_subgroup;
uint32_t vgt_esgs_ring_itemsize; uint32_t vgt_esgs_ring_itemsize;
@@ -390,7 +390,7 @@ struct radv_shader_info {
struct radv_streamout_info so; struct radv_streamout_info so;
struct gfx9_gs_info gs_ring_info; struct radv_legacy_gs_info gs_ring_info;
struct gfx10_ngg_info ngg_info; struct gfx10_ngg_info ngg_info;
}; };

6
src/amd/vulkan/radv_shader_info.c
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@@ -915,13 +915,13 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n
} }
static void static void
gfx9_get_gs_info(const struct radv_device *device, struct radv_pipeline_stage *es_stage, radv_get_legacy_gs_info(const struct radv_device *device, struct radv_pipeline_stage *es_stage,
struct radv_pipeline_stage *gs_stage) struct radv_pipeline_stage *gs_stage)
{ {
const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
struct radv_shader_info *gs_info = &gs_stage->info; struct radv_shader_info *gs_info = &gs_stage->info;
struct radv_shader_info *es_info = &es_stage->info; struct radv_shader_info *es_info = &es_stage->info;
struct gfx9_gs_info *out = &gs_stage->info.gs_ring_info; struct radv_legacy_gs_info *out = &gs_stage->info.gs_ring_info;
const unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1); const unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
const bool uses_adjacency = gs_info->gs.input_prim == SHADER_PRIM_LINES_ADJACENCY || const bool uses_adjacency = gs_info->gs.input_prim == SHADER_PRIM_LINES_ADJACENCY ||
@@ -1402,7 +1402,7 @@ radv_link_shaders_info(struct radv_device *device,
radv_determine_ngg_settings(device, producer, consumer, pipeline_key); radv_determine_ngg_settings(device, producer, consumer, pipeline_key);
} }
} else if (consumer && consumer->stage == MESA_SHADER_GEOMETRY) { } else if (consumer && consumer->stage == MESA_SHADER_GEOMETRY) {
gfx9_get_gs_info(device, producer, consumer); radv_get_legacy_gs_info(device, producer, consumer);
} }
} }