radv: rename gfx9_gs_info to radv_legacy_gs_info
This was misleading because it's also needed on GFX6-8. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22134>
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@@ -5219,7 +5219,7 @@ gfx10_emit_ge_cntl(struct radv_cmd_buffer *cmd_buffer)
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break_wave_at_eoi = true;
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}
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} else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
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const struct gfx9_gs_info *gs_state =
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const struct radv_legacy_gs_info *gs_state =
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&pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
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primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(gs_state->vgt_gs_onchip_cntl);
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} else {
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@@ -1412,8 +1412,9 @@ gfx10_emit_ge_pc_alloc(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level,
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}
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static void
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radv_pipeline_init_gs_ring_state(const struct radv_device *device,
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struct radv_graphics_pipeline *pipeline, const struct gfx9_gs_info *gs)
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radv_pipeline_init_legacy_gs_ring_info(const struct radv_device *device,
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struct radv_graphics_pipeline *pipeline,
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const struct radv_legacy_gs_info *gs)
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{
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const struct radv_physical_device *pdevice = device->physical_device;
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unsigned num_se = pdevice->rad_info.max_se;
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@@ -4036,7 +4037,7 @@ radv_pipeline_emit_hw_gs(const struct radv_device *device, struct radeon_cmdbuf
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const struct radv_shader *gs)
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{
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const struct radv_physical_device *pdevice = device->physical_device;
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const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
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const struct radv_legacy_gs_info *gs_state = &gs->info.gs_ring_info;
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unsigned gs_max_out_vertices;
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const uint8_t *num_components;
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uint8_t max_stream;
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@@ -4967,7 +4968,7 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
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if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) && !radv_pipeline_has_ngg(pipeline)) {
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struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY];
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radv_pipeline_init_gs_ring_state(device, pipeline, &gs->info.gs_ring_info);
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radv_pipeline_init_legacy_gs_ring_info(device, pipeline, &gs->info.gs_ring_info);
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}
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if (!radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH))
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@@ -220,7 +220,7 @@ struct radv_vs_output_info {
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unsigned pos_exports;
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};
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struct gfx9_gs_info {
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struct radv_legacy_gs_info {
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uint32_t vgt_gs_onchip_cntl;
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uint32_t vgt_gs_max_prims_per_subgroup;
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uint32_t vgt_esgs_ring_itemsize;
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@@ -390,7 +390,7 @@ struct radv_shader_info {
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struct radv_streamout_info so;
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struct gfx9_gs_info gs_ring_info;
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struct radv_legacy_gs_info gs_ring_info;
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struct gfx10_ngg_info ngg_info;
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};
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@@ -915,13 +915,13 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n
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}
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static void
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gfx9_get_gs_info(const struct radv_device *device, struct radv_pipeline_stage *es_stage,
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struct radv_pipeline_stage *gs_stage)
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radv_get_legacy_gs_info(const struct radv_device *device, struct radv_pipeline_stage *es_stage,
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struct radv_pipeline_stage *gs_stage)
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{
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const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
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struct radv_shader_info *gs_info = &gs_stage->info;
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struct radv_shader_info *es_info = &es_stage->info;
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struct gfx9_gs_info *out = &gs_stage->info.gs_ring_info;
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struct radv_legacy_gs_info *out = &gs_stage->info.gs_ring_info;
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const unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
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const bool uses_adjacency = gs_info->gs.input_prim == SHADER_PRIM_LINES_ADJACENCY ||
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@@ -1402,7 +1402,7 @@ radv_link_shaders_info(struct radv_device *device,
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radv_determine_ngg_settings(device, producer, consumer, pipeline_key);
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}
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} else if (consumer && consumer->stage == MESA_SHADER_GEOMETRY) {
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gfx9_get_gs_info(device, producer, consumer);
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radv_get_legacy_gs_info(device, producer, consumer);
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}
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}
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