amd: Add and implement sendmsg_amd intrinsic.
This intrinsic is going to be used for simplifying GS code. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Qiang Yu <yuq825@gmail.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
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@@ -9012,6 +9012,12 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr)
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}
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break;
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}
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case nir_intrinsic_sendmsg_amd: {
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unsigned imm = nir_intrinsic_base(instr);
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Temp m0_content = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
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bld.sopp(aco_opcode::s_sendmsg, bld.m0(m0_content), -1, imm);
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break;
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}
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case nir_intrinsic_is_subgroup_invocation_lt_amd: {
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Temp src = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
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bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), lanecount_to_mask(ctx, src));
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@@ -3842,6 +3842,12 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
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case nir_intrinsic_end_primitive_with_counter:
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ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
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break;
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case nir_intrinsic_sendmsg_amd: {
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unsigned imm = nir_intrinsic_base(instr);
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LLVMValueRef m0_content = get_src(ctx, instr->src[0]);
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ac_build_sendmsg(&ctx->ac, imm, m0_content);
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break;
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}
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case nir_intrinsic_load_tess_coord: {
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LLVMValueRef coord[] = {
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ctx->abi->tes_u_replaced ? ctx->abi->tes_u_replaced : ac_get_arg(&ctx->ac, ctx->args->tes_u),
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@@ -1478,6 +1478,8 @@ intrinsic("load_cull_small_prim_precision_amd", dest_comp=1, bit_sizes=[32], fla
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intrinsic("load_initial_edgeflags_amd", src_comp=[], dest_comp=1, bit_sizes=[32], indices=[])
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# Allocates export space for vertices and primitives. src[] = {num_vertices, num_primitives}.
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intrinsic("alloc_vertices_and_primitives_amd", src_comp=[1, 1], indices=[])
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# Corresponds to s_sendmsg in the GCN/RDNA ISA, src[] = { m0_content }, BASE = imm
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intrinsic("sendmsg_amd", src_comp=[1], indices=[BASE])
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# Overwrites VS input registers, for use with vertex compaction after culling. src = {vertex_id, instance_id}.
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intrinsic("overwrite_vs_arguments_amd", src_comp=[1, 1], indices=[])
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# Overwrites TES input registers, for use with vertex compaction after culling. src = {tes_u, tes_v, rel_patch_id, patch_id}.
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