freedreno: Add some missing a6xx address declarations.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3455>
This commit is contained in:
Eric Anholt
2020-01-16 16:05:06 -08:00
committed by Marge Bot
parent 4b7de92e5f
commit c1327bc283

View File

@@ -1998,6 +1998,7 @@ to upconvert to 32b float internally?
</reg32>
<reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
<reg32 offset="0x8107" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
<reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" type="waddress"/>
<reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL">
<bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
@@ -2483,11 +2484,13 @@ to upconvert to 32b float internally?
<reg32 offset="0x9219" name="VPC_SO_STREAM_COUNTS_HI"/>
<array offset="0x921a" name="VPC_SO" stride="7" length="4">
<reg64 offset="0" name="BUFFER_BASE" type="waddress"/>
<reg32 offset="0" name="BUFFER_BASE_LO"/>
<reg32 offset="1" name="BUFFER_BASE_HI"/>
<reg32 offset="2" name="BUFFER_SIZE"/>
<reg32 offset="3" name="NCOMP"/> <!-- component count -->
<reg32 offset="4" name="BUFFER_OFFSET"/>
<reg64 offset="5" name="FLUSH_BASE" type="waddress"/>
<reg32 offset="5" name="FLUSH_BASE_LO"/>
<reg32 offset="6" name="FLUSH_BASE_HI"/>
</array>
@@ -2717,6 +2720,7 @@ to upconvert to 32b float internally?
<reg32 offset="0xa00e" name="VFD_INDEX_OFFSET"/>
<reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET"/>
<array offset="0xa010" name="VFD_FETCH" stride="4" length="32">
<reg64 offset="0x0" name="BASE" type="address"/>
<reg32 offset="0x0" name="BASE_LO"/>
<reg32 offset="0x1" name="BASE_HI"/>
<reg32 offset="0x2" name="SIZE" type="uint"/>
@@ -3081,6 +3085,7 @@ to upconvert to 32b float internally?
</reg32>
<!-- looks to work in the same way as a5xx: -->
<reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
<reg32 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR_LO"/>
<reg32 offset="0xb303" name="SP_TP_BORDER_COLOR_BASE_ADDR_HI"/>
<!-- always 0x0 ? -->