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intel/nir: Add a common nir comparison -> cmod helper

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We already had one in the vec4 code, we just had move it.

Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Jason Ekstrand
2019-08-02 15:19:16 -05:00
parent 2fd30e3722
commit c02c3ff612
4 changed files with 47 additions and 82 deletions
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42
src/intel/compiler/brw_fs_nir.cpp
View File

@@ -1298,25 +1298,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
if (bit_size != 32)
dest = bld.vgrf(op[0].type, 1);
brw_conditional_mod cond;
switch (instr->op) {
case nir_op_flt32:
cond = BRW_CONDITIONAL_L;
break;
case nir_op_fge32:
cond = BRW_CONDITIONAL_GE;
break;
case nir_op_feq32:
cond = BRW_CONDITIONAL_Z;
break;
case nir_op_fne32:
cond = BRW_CONDITIONAL_NZ;
break;
default:
unreachable("bad opcode");
}
bld.CMP(dest, op[0], op[1], cond);
bld.CMP(dest, op[0], op[1], brw_cmod_for_nir_comparison(instr->op));
if (bit_size > 32) {
bld.MOV(result, subscript(dest, BRW_REGISTER_TYPE_UD, 0));
@@ -1351,26 +1333,8 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
if (bit_size != 32)
dest = bld.vgrf(temp_op[0].type, 1);
brw_conditional_mod cond;
switch (instr->op) {
case nir_op_ilt32:
case nir_op_ult32:
cond = BRW_CONDITIONAL_L;
break;
case nir_op_ige32:
case nir_op_uge32:
cond = BRW_CONDITIONAL_GE;
break;
case nir_op_ieq32:
cond = BRW_CONDITIONAL_Z;
break;
case nir_op_ine32:
cond = BRW_CONDITIONAL_NZ;
break;
default:
unreachable("bad opcode");
}
bld.CMP(dest, temp_op[0], temp_op[1], cond);
bld.CMP(dest, temp_op[0], temp_op[1],
brw_cmod_for_nir_comparison(instr->op));
if (bit_size > 32) {
bld.MOV(result, subscript(dest, BRW_REGISTER_TYPE_UD, 0));

39
src/intel/compiler/brw_nir.c
View File

@@ -1041,6 +1041,45 @@ brw_nir_apply_key(nir_shader *nir,
brw_nir_optimize(nir, compiler, is_scalar, false);
}
enum brw_conditional_mod
brw_cmod_for_nir_comparison(nir_op op)
{
switch (op) {
case nir_op_flt32:
case nir_op_ilt32:
case nir_op_ult32:
return BRW_CONDITIONAL_L;
case nir_op_fge32:
case nir_op_ige32:
case nir_op_uge32:
return BRW_CONDITIONAL_GE;
case nir_op_feq32:
case nir_op_ieq32:
case nir_op_b32all_fequal2:
case nir_op_b32all_iequal2:
case nir_op_b32all_fequal3:
case nir_op_b32all_iequal3:
case nir_op_b32all_fequal4:
case nir_op_b32all_iequal4:
return BRW_CONDITIONAL_Z;
case nir_op_fne32:
case nir_op_ine32:
case nir_op_b32any_fnequal2:
case nir_op_b32any_inequal2:
case nir_op_b32any_fnequal3:
case nir_op_b32any_inequal3:
case nir_op_b32any_fnequal4:
case nir_op_b32any_inequal4:
return BRW_CONDITIONAL_NZ;
default:
unreachable("Unsupported NIR comparison op");
}
}
enum brw_reg_type
brw_type_for_nir_type(const struct gen_device_info *devinfo, nir_alu_type type)
{

1
src/intel/compiler/brw_nir.h
View File

@@ -146,6 +146,7 @@ void brw_nir_apply_key(nir_shader *nir,
unsigned max_subgroup_size,
bool is_scalar);
enum brw_conditional_mod brw_cmod_for_nir_comparison(nir_op op);
enum brw_reg_type brw_type_for_nir_type(const struct gen_device_info *devinfo,
nir_alu_type type);

47
src/intel/compiler/brw_vec4_nir.cpp
View File

@@ -786,45 +786,6 @@ brw_swizzle_for_nir_swizzle(uint8_t swizzle[4])
return BRW_SWIZZLE4(swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
}
static enum brw_conditional_mod
brw_conditional_for_nir_comparison(nir_op op)
{
switch (op) {
case nir_op_flt32:
case nir_op_ilt32:
case nir_op_ult32:
return BRW_CONDITIONAL_L;
case nir_op_fge32:
case nir_op_ige32:
case nir_op_uge32:
return BRW_CONDITIONAL_GE;
case nir_op_feq32:
case nir_op_ieq32:
case nir_op_b32all_fequal2:
case nir_op_b32all_iequal2:
case nir_op_b32all_fequal3:
case nir_op_b32all_iequal3:
case nir_op_b32all_fequal4:
case nir_op_b32all_iequal4:
return BRW_CONDITIONAL_Z;
case nir_op_fne32:
case nir_op_ine32:
case nir_op_b32any_fnequal2:
case nir_op_b32any_inequal2:
case nir_op_b32any_fnequal3:
case nir_op_b32any_inequal3:
case nir_op_b32any_fnequal4:
case nir_op_b32any_inequal4:
return BRW_CONDITIONAL_NZ;
default:
unreachable("not reached: bad operation for comparison");
}
}
bool
vec4_visitor::optimize_predicate(nir_alu_instr *instr,
enum brw_predicate *predicate)
@@ -875,7 +836,7 @@ vec4_visitor::optimize_predicate(nir_alu_instr *instr,
}
emit(CMP(dst_null_d(), op[0], op[1],
brw_conditional_for_nir_comparison(cmp_instr->op)));
brw_cmod_for_nir_comparison(cmp_instr->op)));
return true;
}
@@ -1529,7 +1490,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
case nir_op_feq32:
case nir_op_fne32: {
enum brw_conditional_mod conditional_mod =
brw_conditional_for_nir_comparison(instr->op);
brw_cmod_for_nir_comparison(instr->op);
if (nir_src_bit_size(instr->src[0].src) < 64) {
/* If the order of the sources is changed due to an immediate value,
@@ -1566,7 +1527,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
brw_swizzle_for_size(nir_op_infos[instr->op].input_sizes[0]);
emit(CMP(dst_null_d(), swizzle(op[0], swiz), swizzle(op[1], swiz),
brw_conditional_for_nir_comparison(instr->op)));
brw_cmod_for_nir_comparison(instr->op)));
emit(MOV(dst, brw_imm_d(0)));
inst = emit(MOV(dst, brw_imm_d(~0)));
inst->predicate = BRW_PREDICATE_ALIGN16_ALL4H;
@@ -1585,7 +1546,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
brw_swizzle_for_size(nir_op_infos[instr->op].input_sizes[0]);
emit(CMP(dst_null_d(), swizzle(op[0], swiz), swizzle(op[1], swiz),
brw_conditional_for_nir_comparison(instr->op)));
brw_cmod_for_nir_comparison(instr->op)));
emit(MOV(dst, brw_imm_d(0)));
inst = emit(MOV(dst, brw_imm_d(~0)));