diff --git a/docs/gallium/screen.rst b/docs/gallium/screen.rst index c42d9656131..d1a772e9281 100644 --- a/docs/gallium/screen.rst +++ b/docs/gallium/screen.rst @@ -456,8 +456,6 @@ The integer capabilities: * ``PIPE_CAP_MEMOBJ``: Whether operations on memory objects are supported. * ``PIPE_CAP_LOAD_CONSTBUF``: True if the driver supports ``TGSI_OPCODE_LOAD`` use with constant buffers. -* ``PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS``: Any TGSI register can be used as - an address for indirect register indexing. * ``PIPE_CAP_TILE_RASTER_ORDER``: Whether the driver supports GL_MESA_tile_raster_order, using the tile_raster_order_* fields in pipe_rasterizer_state. diff --git a/src/gallium/auxiliary/nir/nir_to_tgsi.c b/src/gallium/auxiliary/nir/nir_to_tgsi.c index 549cfea7804..5ad01306fbd 100644 --- a/src/gallium/auxiliary/nir/nir_to_tgsi.c +++ b/src/gallium/auxiliary/nir/nir_to_tgsi.c @@ -41,7 +41,6 @@ struct ntt_compile { struct ureg_program *ureg; bool needs_texcoord_semantic; - bool any_reg_as_address; bool native_integers; bool has_txf_lz; @@ -632,9 +631,6 @@ ntt_get_load_const_src(struct ntt_compile *c, nir_load_const_instr *instr) static struct ureg_src ntt_reladdr(struct ntt_compile *c, struct ureg_src addr, int addr_index) { - if (c->any_reg_as_address) - return ureg_scalar(addr, 0); - for (int i = 0; i <= addr_index; i++) { if (!c->addr_declared[i]) { c->addr_reg[i] = ureg_writemask(ureg_DECL_address(c->ureg), @@ -3143,8 +3139,6 @@ nir_to_tgsi(struct nir_shader *s, c->needs_texcoord_semantic = screen->get_param(screen, PIPE_CAP_TGSI_TEXCOORD); - c->any_reg_as_address = - screen->get_param(screen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS); c->has_txf_lz = screen->get_param(screen, PIPE_CAP_TGSI_TEX_TXF_LZ); diff --git a/src/gallium/auxiliary/util/u_screen.c b/src/gallium/auxiliary/util/u_screen.c index 907026f5642..8eaa83be572 100644 --- a/src/gallium/auxiliary/util/u_screen.c +++ b/src/gallium/auxiliary/util/u_screen.c @@ -333,7 +333,6 @@ u_pipe_screen_get_param_defaults(struct pipe_screen *pscreen, case PIPE_CAP_QUERY_SO_OVERFLOW: case PIPE_CAP_MEMOBJ: case PIPE_CAP_LOAD_CONSTBUF: - case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS: case PIPE_CAP_TILE_RASTER_ORDER: return 0; diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c b/src/gallium/drivers/nouveau/nv30/nv30_screen.c index 4d6a0749931..8b43357a375 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c @@ -237,7 +237,6 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_QUERY_SO_OVERFLOW: case PIPE_CAP_MEMOBJ: case PIPE_CAP_LOAD_CONSTBUF: - case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS: case PIPE_CAP_TILE_RASTER_ORDER: case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES: case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS: diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c b/src/gallium/drivers/nouveau/nv50/nv50_screen.c index 6b2441281c8..34469dde6f1 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c @@ -345,7 +345,6 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_QUERY_SO_OVERFLOW: case PIPE_CAP_MEMOBJ: case PIPE_CAP_LOAD_CONSTBUF: - case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS: case PIPE_CAP_TILE_RASTER_ORDER: case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS: case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET: diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index 5af05601864..9e6b09845a2 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -389,7 +389,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_NIR_SAMPLERS_AS_DEREF: case PIPE_CAP_MEMOBJ: case PIPE_CAP_LOAD_CONSTBUF: - case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS: case PIPE_CAP_TILE_RASTER_ORDER: case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES: case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS: diff --git a/src/gallium/drivers/softpipe/sp_screen.c b/src/gallium/drivers/softpipe/sp_screen.c index 122e54e0cf5..c87d4067cfc 100644 --- a/src/gallium/drivers/softpipe/sp_screen.c +++ b/src/gallium/drivers/softpipe/sp_screen.c @@ -289,7 +289,6 @@ softpipe_get_param(struct pipe_screen *screen, enum pipe_cap param) case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: case PIPE_CAP_TGSI_ARRAY_COMPONENTS: case PIPE_CAP_TGSI_TEXCOORD: - case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS: return 1; case PIPE_CAP_CLEAR_TEXTURE: return 1; diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h index 4c5e29e79b6..fa46cd59c04 100644 --- a/src/gallium/include/pipe/p_defines.h +++ b/src/gallium/include/pipe/p_defines.h @@ -905,7 +905,6 @@ enum pipe_cap PIPE_CAP_QUERY_SO_OVERFLOW, PIPE_CAP_MEMOBJ, PIPE_CAP_LOAD_CONSTBUF, - PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS, PIPE_CAP_TILE_RASTER_ORDER, PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES, PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS, diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index 9236f8f25ac..0cf4de55072 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -381,7 +381,6 @@ public: bool use_shared_memory; bool has_tex_txf_lz; bool precise; - bool need_uarl; bool tg4_component_in_swizzle; variable_storage *find_variable_storage(ir_variable *var); @@ -1093,9 +1092,6 @@ glsl_to_tgsi_visitor::emit_arl(ir_instruction *ir, enum tgsi_opcode op = TGSI_OPCODE_ARL; if (src0.type == GLSL_TYPE_INT || src0.type == GLSL_TYPE_UINT) { - if (!this->need_uarl && src0.is_legal_tgsi_address_operand()) - return; - op = TGSI_OPCODE_UARL; } @@ -4966,7 +4962,6 @@ glsl_to_tgsi_visitor::glsl_to_tgsi_visitor() ctx = NULL; prog = NULL; precise = 0; - need_uarl = false; tg4_component_in_swizzle = false; shader_program = NULL; shader = NULL; @@ -6024,7 +6019,6 @@ struct st_translate { const ubyte *outputMapping; enum pipe_shader_type procType; /**< PIPE_SHADER_VERTEX/FRAGMENT */ - bool need_uarl; bool tg4_component_in_swizzle; }; @@ -6145,10 +6139,7 @@ static struct ureg_src translate_addr(struct st_translate *t, const st_src_reg *reladdr, unsigned addr_index) { - if (t->need_uarl || !reladdr->is_legal_tgsi_address_operand()) - return ureg_src(t->address[addr_index]); - - return translate_src(t, reladdr); + return ureg_src(t->address[addr_index]); } /** @@ -6852,7 +6843,6 @@ st_translate_program( } t->procType = procType; - t->need_uarl = !screen->get_param(screen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS); t->tg4_component_in_swizzle = screen->get_param(screen, PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE); t->inputMapping = inputMapping; t->outputMapping = outputMapping; @@ -7266,7 +7256,6 @@ get_mesa_program_tgsi(struct gl_context *ctx, PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED); v->has_tex_txf_lz = pscreen->get_param(pscreen, PIPE_CAP_TGSI_TEX_TXF_LZ); - v->need_uarl = !pscreen->get_param(pscreen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS); v->tg4_component_in_swizzle = pscreen->get_param(pscreen, PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE); v->variables = _mesa_hash_table_create(v->mem_ctx, _mesa_hash_pointer,