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intel/genxml: add missing power well control bits

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Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20782>
This commit is contained in:
Dave Airlie
2023-02-07 08:22:23 +10:00
committed by Marge Bot
parent cfc62802f8
commit bff627142d
2 changed files with 4 additions and 0 deletions
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2
src/intel/genxml/gen12.xml
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@@ -5884,6 +5884,8 @@
<field name="Force Media-Slice1 Awake" start="34" end="34" type="uint" />
<field name="Force Media-Slice2 Awake" start="35" end="35" type="uint" />
<field name="Force Media-Slice3 Awake" start="36" end="36" type="uint" />
<field name="HEVC Power Well Control" start="40" end="40" type="bool" />
<field name="MFX Power Well Control" start="41" end="41" type="bool" />
<field name="Mask Bits" start="48" end="63" type="uint" />
</instruction>
<instruction name="MI_LOAD_REGISTER_IMM" bias="2" length="3">

2
src/intel/genxml/gen125.xml
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@@ -6237,6 +6237,8 @@
<field name="Force Media-Slice1 Awake" start="34" end="34" type="uint" />
<field name="Force Media-Slice2 Awake" start="35" end="35" type="uint" />
<field name="Force Media-Slice3 Awake" start="36" end="36" type="uint" />
<field name="HEVC Power Well Control" start="40" end="40" type="bool" />
<field name="MFX Power Well Control" start="41" end="41" type="bool" />
<field name="Mask Bits" start="48" end="63" type="uint" />
</instruction>
<instruction name="MI_LOAD_REGISTER_IMM" bias="2" length="3">