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radv/tess: remove last chunk of tess sgprs

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This removes the last TES-specifc user sgpr.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie
2018-02-19 19:15:25 +00:00
parent 6db44d6a8c
commit bf9a0ea853
3 changed files with 19 additions and 53 deletions
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50
src/amd/vulkan/radv_nir_to_llvm.c
View File

@@ -62,7 +62,6 @@ struct radv_shader_context {
LLVMValueRef vs_prim_id; LLVMValueRef vs_prim_id;
LLVMValueRef es2gs_offset; LLVMValueRef es2gs_offset;
LLVMValueRef tcs_offchip_layout;
LLVMValueRef oc_lds; LLVMValueRef oc_lds;
LLVMValueRef merged_wave_info; LLVMValueRef merged_wave_info;
LLVMValueRef tess_factor_offset; LLVMValueRef tess_factor_offset;
@@ -533,14 +532,11 @@ static void allocate_user_sgprs(struct radv_shader_context *ctx,
} }
break; break;
case MESA_SHADER_TESS_EVAL: case MESA_SHADER_TESS_EVAL:
user_sgpr_info->sgpr_count += 1;
break; break;
case MESA_SHADER_GEOMETRY: case MESA_SHADER_GEOMETRY:
if (has_previous_stage) { if (has_previous_stage) {
if (previous_stage == MESA_SHADER_VERTEX) { if (previous_stage == MESA_SHADER_VERTEX) {
user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx); user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
} else {
user_sgpr_info->sgpr_count++;
} }
} }
user_sgpr_info->sgpr_count += 2; user_sgpr_info->sgpr_count += 2;
@@ -861,7 +857,6 @@ static void create_function(struct radv_shader_context *ctx,
previous_stage, &user_sgpr_info, previous_stage, &user_sgpr_info,
&args, &desc_sets); &args, &desc_sets);
add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
if (needs_view_index) if (needs_view_index)
add_arg(&args, ARG_SGPR, ctx->ac.i32, add_arg(&args, ARG_SGPR, ctx->ac.i32,
&ctx->abi.view_index); &ctx->abi.view_index);
@@ -896,10 +891,7 @@ static void create_function(struct radv_shader_context *ctx,
&user_sgpr_info, &args, &user_sgpr_info, &args,
&desc_sets); &desc_sets);
if (previous_stage == MESA_SHADER_TESS_EVAL) { if (previous_stage != MESA_SHADER_TESS_EVAL) {
add_arg(&args, ARG_SGPR, ctx->ac.i32,
&ctx->tcs_offchip_layout);
} else {
declare_vs_specific_input_sgprs(ctx, stage, declare_vs_specific_input_sgprs(ctx, stage,
has_previous_stage, has_previous_stage,
previous_stage, previous_stage,
@@ -1055,7 +1047,6 @@ static void create_function(struct radv_shader_context *ctx,
set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1); set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
break; break;
case MESA_SHADER_TESS_EVAL: case MESA_SHADER_TESS_EVAL:
set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
if (ctx->abi.view_index) if (ctx->abi.view_index)
set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1); set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
break; break;
@@ -1066,9 +1057,6 @@ static void create_function(struct radv_shader_context *ctx,
has_previous_stage, has_previous_stage,
previous_stage, previous_stage,
&user_sgpr_idx); &user_sgpr_idx);
else
set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
&user_sgpr_idx, 1);
} }
set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
&user_sgpr_idx, 2); &user_sgpr_idx, 2);
@@ -1149,35 +1137,27 @@ radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
*/ */
static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx) static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
{ {
if (ctx->stage == MESA_SHADER_TESS_CTRL) { uint32_t num_patches = ctx->tcs_num_patches;
uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written); uint32_t num_tcs_outputs;
uint32_t output_vertex_size = num_tcs_outputs * 16; if (ctx->stage == MESA_SHADER_TESS_CTRL)
uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size; num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
uint32_t num_patches = ctx->tcs_num_patches; else
num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false); uint32_t output_vertex_size = num_tcs_outputs * 16;
} else uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
return ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
} }
static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx, static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
LLVMValueRef vertex_index) LLVMValueRef vertex_index)
{ {
LLVMValueRef param_stride; LLVMValueRef param_stride;
if (ctx->stage == MESA_SHADER_TESS_CTRL) { if (vertex_index)
if (vertex_index) param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch * ctx->tcs_num_patches, false);
param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch * ctx->tcs_num_patches, false); else
else param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
} else {
LLVMValueRef num_patches = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
if (vertex_index)
param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
num_patches, "");
else
param_stride = num_patches;
}
return param_stride; return param_stride;
} }

18
src/amd/vulkan/radv_pipeline.c
View File

@@ -62,7 +62,6 @@ struct radv_blend_state {
struct radv_tessellation_state { struct radv_tessellation_state {
uint32_t ls_hs_config; uint32_t ls_hs_config;
uint32_t offchip_layout;
unsigned num_patches; unsigned num_patches;
unsigned lds_size; unsigned lds_size;
uint32_t tf_param; uint32_t tf_param;
@@ -1378,9 +1377,6 @@ calculate_tess_state(struct radv_pipeline *pipeline,
tess.lds_size = lds_size; tess.lds_size = lds_size;
tess.offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
num_patches;
tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) | tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) | S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp); S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
@@ -1786,6 +1782,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
} }
modules[MESA_SHADER_VERTEX] = NULL; modules[MESA_SHADER_VERTEX] = NULL;
keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches; keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
} }
if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) { if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
@@ -1807,6 +1804,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
} }
if (i == MESA_SHADER_TESS_EVAL) { if (i == MESA_SHADER_TESS_EVAL) {
keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches; keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
} }
pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1, pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
pipeline->layout, pipeline->layout,
@@ -2605,18 +2603,6 @@ radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
else else
radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
tess->ls_hs_config); tess->ls_hs_config);
struct radv_userdata_info *loc;
loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
if (loc->sgpr_idx != -1) {
uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
assert(loc->num_sgprs == 1);
assert(!loc->indirect);
radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4,
tess->offchip_layout);
}
} }
static void static void

4
src/amd/vulkan/radv_shader.h
View File

@@ -63,7 +63,8 @@ struct radv_vs_variant_key {
struct radv_tes_variant_key { struct radv_tes_variant_key {
uint32_t as_es:1; uint32_t as_es:1;
uint32_t export_prim_id:1; uint32_t export_prim_id:1;
uint32_t num_patches; uint8_t num_patches;
uint8_t tcs_num_outputs;
}; };
struct radv_tcs_variant_key { struct radv_tcs_variant_key {
@@ -123,7 +124,6 @@ enum radv_ud_index {
AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_VS_MAX_UD, AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_VS_MAX_UD,
AC_UD_GS_MAX_UD, AC_UD_GS_MAX_UD,
AC_UD_TCS_MAX_UD, AC_UD_TCS_MAX_UD,
AC_UD_TES_OFFCHIP_LAYOUT = AC_UD_SHADER_START,
AC_UD_TES_MAX_UD, AC_UD_TES_MAX_UD,
AC_UD_MAX_UD = AC_UD_TCS_MAX_UD, AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
}; };