OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

i965/miptree: Clean-up unused

Browse Source 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Topi Pohjolainen
2017-06-20 21:20:15 +03:00
parent f5859b45b1
commit bf24c3539e
14 changed files with 95 additions and 1645 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/mesa/drivers/dri/i965/Makefile.sources
View File

@@ -51,7 +51,6 @@ i965_FILES = \
brw_tcs_surface_state.c \
brw_tes.c \
brw_tes_surface_state.c \
brw_tex_layout.c \
brw_urb.c \
brw_util.c \
brw_util.h \

8
src/mesa/drivers/dri/i965/brw_blorp.c
View File

@@ -147,13 +147,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
intel_miptree_check_level_layer(mt, *level, start_layer + i);
}
if (mt->surf.size > 0) {
surf->surf = &mt->surf;
} else {
intel_miptree_get_isl_surf(brw, mt, &tmp_surfs[0]);
surf->surf = &tmp_surfs[0];
}
surf->surf = &mt->surf;
surf->addr = (struct blorp_address) {
.buffer = mt->bo,
.offset = mt->offset,

735
src/mesa/drivers/dri/i965/brw_tex_layout.c
View File

@@ -1,735 +0,0 @@
/*
* Copyright 2006 VMware, Inc.
* Copyright © 2006 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/**
* \file brw_tex_layout.cpp
*
* Code to lay out images in a mipmap tree.
*
* \author Keith Whitwell <keithw@vmware.com>
* \author Michel Dänzer <daenzer@vmware.com>
*/
#include "intel_mipmap_tree.h"
#include "brw_context.h"
#include "main/macros.h"
#include "main/glformats.h"
#define FILE_DEBUG_FLAG DEBUG_MIPTREE
static unsigned int
intel_horizontal_texture_alignment_unit(struct brw_context *brw,
struct intel_mipmap_tree *mt,
uint32_t layout_flags)
{
if (layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16)
return 16;
/**
* +----------------------------------------------------------------------+
* | | alignment unit width ("i") |
* | Surface Property |-----------------------------|
* | | 915 | 965 | ILK | SNB | IVB |
* +----------------------------------------------------------------------+
* | YUV 4:2:2 format | 8 | 4 | 4 | 4 | 4 |
* | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
* | FXT1 compressed format | 8 | 8 | 8 | 8 | 8 |
* | Depth Buffer (16-bit) | 4 | 4 | 4 | 4 | 8 |
* | Depth Buffer (other) | 4 | 4 | 4 | 4 | 4 |
* | Separate Stencil Buffer | N/A | N/A | 8 | 8 | 8 |
* | All Others | 4 | 4 | 4 | 4 | 4 |
* +----------------------------------------------------------------------+
*
* On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
* "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
*/
if (brw->gen >= 7 && mt->format == MESA_FORMAT_Z_UNORM16)
return 8;
return 4;
}
static unsigned int
intel_vertical_texture_alignment_unit(struct brw_context *brw,
const struct intel_mipmap_tree *mt)
{
/**
* +----------------------------------------------------------------------+
* | | alignment unit height ("j") |
* | Surface Property |-----------------------------|
* | | 915 | 965 | ILK | SNB | IVB |
* +----------------------------------------------------------------------+
* | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
* | FXT1 compressed format | 4 | 4 | 4 | 4 | 4 |
* | Depth Buffer | 2 | 2 | 2 | 4 | 4 |
* | Separate Stencil Buffer | N/A | N/A | N/A | 4 | 8 |
* | Multisampled (4x or 8x) render target | N/A | N/A | N/A | 4 | 4 |
* | All Others | 2 | 2 | 2 | * | * |
* +----------------------------------------------------------------------+
*
* Where "*" means either VALIGN_2 or VALIGN_4 depending on the setting of
* the SURFACE_STATE "Surface Vertical Alignment" field.
*/
/* Broadwell only supports VALIGN of 4, 8, and 16. The BSpec says 4
* should always be used, except for stencil buffers, which should be 8.
*/
if (brw->gen >= 8)
return 4;
if (mt->surf.samples > 1)
return 4;
GLenum base_format = _mesa_get_format_base_format(mt->format);
if (brw->gen >= 6 &&
(base_format == GL_DEPTH_COMPONENT ||
base_format == GL_DEPTH_STENCIL)) {
return 4;
}
if (brw->gen == 7) {
/* On Gen7, we prefer a vertical alignment of 4 when possible, because
* that allows Y tiled render targets.
*
* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
* messages), on p64, under the heading "Surface Vertical Alignment":
*
* Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
* (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
* (0x190)
*
* VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
*/
if (base_format == GL_YCBCR_MESA || mt->format == MESA_FORMAT_RGB_FLOAT32)
return 2;
return 4;
}
return 2;
}
static void
gen9_miptree_layout_1d(struct intel_mipmap_tree *mt)
{
unsigned x = 0;
unsigned width = mt->physical_width0;
unsigned depth = mt->physical_depth0; /* number of array layers. */
/* When this layout is used the horizontal alignment is fixed at 64 and the
* hardware ignores the value given in the surface state
*/
const unsigned int halign = 64;
mt->total_height = mt->physical_height0;
mt->total_width = 0;
for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
unsigned img_width;
intel_miptree_set_level_info(mt, level, x, 0, depth);
img_width = ALIGN(width, halign);
mt->total_width = MAX2(mt->total_width, x + img_width);
x += img_width;
width = minify(width, 1);
}
}
static void
brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
{
unsigned x = 0;
unsigned y = 0;
unsigned width = mt->physical_width0;
unsigned height = mt->physical_height0;
/* Number of layers of array texture or slices of 3d texture (gen9+). */
unsigned depth = mt->physical_depth0;
unsigned int bw, bh;
_mesa_get_format_block_size(mt->format, &bw, &bh);
mt->total_width = mt->physical_width0;
mt->total_width = ALIGN_NPOT(mt->total_width, bw);
/* May need to adjust width to accommodate the placement of
* the 2nd mipmap. This occurs when the alignment
* constraints of mipmap placement push the right edge of the
* 2nd mipmap out past the width of its parent.
*/
if (mt->first_level != mt->last_level) {
unsigned mip1_width;
mip1_width = ALIGN_NPOT(minify(mt->physical_width0, 1), mt->halign) +
ALIGN_NPOT(minify(mt->physical_width0, 2), bw);
if (mip1_width > mt->total_width)
mt->total_width = mip1_width;
}
mt->total_width /= bw;
mt->total_height = 0;
for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
unsigned img_height;
intel_miptree_set_level_info(mt, level, x, y, depth);
img_height = ALIGN_NPOT(height, mt->valign);
img_height /= bh;
if (mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
/* Compact arrays with separated miplevels */
img_height *= depth;
}
/* Because the images are packed better, the final offset
* might not be the maximal one:
*/
mt->total_height = MAX2(mt->total_height, y + img_height);
/* Layout_below: step right after second mipmap.
*
* For Sandy Bridge HiZ and stencil, we always step down.
*/
if (level == mt->first_level + 1) {
x += ALIGN_NPOT(width, mt->halign) / bw;
} else {
y += img_height;
}
width = minify(width, 1);
height = minify(height, 1);
if (mt->target == GL_TEXTURE_3D)
depth = minify(depth, 1);
}
}
static void
brw_miptree_layout_gen6_hiz_stencil(struct intel_mipmap_tree *mt)
{
unsigned x = 0;
unsigned y = 0;
unsigned width = mt->physical_width0;
unsigned height = mt->physical_height0;
/* Number of layers of array texture. */
unsigned depth = mt->physical_depth0;
unsigned tile_width, tile_height, bw, bh;
if (mt->format == MESA_FORMAT_S_UINT8) {
bw = bh = 1;
/* W-tiled */
tile_width = 64;
tile_height = 64;
} else {
assert(_mesa_get_format_base_format(mt->format) == GL_DEPTH_COMPONENT ||
_mesa_get_format_base_format(mt->format) == GL_DEPTH_STENCIL);
/* Each 128-bit HiZ block corresponds to a region of of 8x4 depth
* samples. Each cache line in the Y-Tiled HiZ image contains 2x2 HiZ
* blocks. Therefore, each Y-tiled cache line corresponds to an 16x8
* region in the depth surface. Since we're representing it as
* RGBA_FLOAT32, the miptree calculations will think that each cache
* line is 1x4 pixels. Therefore, we need a scale-down factor of 16x2
* and a vertical alignment of 2.
*/
mt->cpp = 16;
bw = 16;
bh = 2;
/* Y-tiled */
tile_width = 128 / mt->cpp;
tile_height = 32;
}
mt->total_width = 0;
mt->total_height = 0;
for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
intel_miptree_set_level_info(
mt, level, x, y,
mt->target == GL_TEXTURE_3D ? minify(depth, level) : depth);
const unsigned img_width = ALIGN(DIV_ROUND_UP(width, bw), mt->halign);
const unsigned img_height =
ALIGN(DIV_ROUND_UP(height, bh), mt->valign) * depth;
mt->total_width = MAX2(mt->total_width, x + img_width);
mt->total_height = MAX2(mt->total_height, y + img_height);
if (level == mt->first_level) {
y += ALIGN(img_height, tile_height);
} else {
x += ALIGN(img_width, tile_width);
}
/* We only minify the width. We want qpitch to match for all miplevels
* because the hardware doesn't know we aren't on LOD0.
*/
width = minify(width, 1);
}
}
unsigned
brw_miptree_get_horizontal_slice_pitch(const struct brw_context *brw,
const struct intel_mipmap_tree *mt,
unsigned level)
{
if ((brw->gen < 9 && mt->target == GL_TEXTURE_3D) ||
(brw->gen == 4 && mt->target == GL_TEXTURE_CUBE_MAP)) {
return ALIGN_NPOT(minify(mt->physical_width0, level), mt->halign);
} else {
return 0;
}
}
static unsigned
brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw,
const struct intel_mipmap_tree *mt,
unsigned level)
{
assert(mt->array_layout != GEN6_HIZ_STENCIL || brw->gen == 6);
if (brw->gen >= 9) {
/* ALL_SLICES_AT_EACH_LOD isn't supported on Gen8+ but this code will
* effectively end up with a packed qpitch anyway whenever
* mt->first_level == mt->last_level.
*/
assert(mt->array_layout != ALL_SLICES_AT_EACH_LOD);
/* On Gen9 we can pick whatever qpitch we like as long as it's aligned
* to the vertical alignment so we don't need to add any extra rows.
*/
unsigned qpitch = mt->total_height;
/* If the surface might be used as a stencil buffer or HiZ buffer then
* it needs to be a multiple of 8.
*/
const GLenum base_format = _mesa_get_format_base_format(mt->format);
if (_mesa_is_depth_or_stencil_format(base_format))
qpitch = ALIGN(qpitch, 8);
/* 3D textures need to be aligned to the tile height. At this point we
* don't know which tiling will be used so let's just align it to 32
*/
if (mt->target == GL_TEXTURE_3D)
qpitch = ALIGN(qpitch, 32);
return qpitch;
} else if (mt->target == GL_TEXTURE_3D ||
(brw->gen == 4 && mt->target == GL_TEXTURE_CUBE_MAP) ||
mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
return ALIGN_NPOT(minify(mt->physical_height0, level), mt->valign);
} else if (mt->array_layout == GEN6_HIZ_STENCIL) {
/* For HiZ and stencil on Sandy Bridge, we don't minify the height. */
if (mt->format == MESA_FORMAT_S_UINT8) {
return ALIGN(mt->physical_height0, mt->valign);
} else {
/* HiZ has a vertical scale factor of 2. */
return ALIGN(DIV_ROUND_UP(mt->physical_height0, 2), mt->valign);
}
} else {
const unsigned h0 = ALIGN_NPOT(mt->physical_height0, mt->valign);
const unsigned h1 = ALIGN_NPOT(minify(mt->physical_height0, 1), mt->valign);
return h0 + h1 + (brw->gen >= 7 ? 12 : 11) * mt->valign;
}
}
static void
align_cube(struct intel_mipmap_tree *mt)
{
/* The 965's sampler lays cachelines out according to how accesses
* in the texture surfaces run, so they may be "vertical" through
* memory. As a result, the docs say in Surface Padding Requirements:
* Sampling Engine Surfaces that two extra rows of padding are required.
*/
if (mt->target == GL_TEXTURE_CUBE_MAP)
mt->total_height += 2;
}
bool
gen9_use_linear_1d_layout(const struct brw_context *brw,
const struct intel_mipmap_tree *mt)
{
/* On Gen9+ the mipmap levels of a 1D surface are all laid out in a
* horizontal line. This isn't done for depth/stencil buffers however
* because those will be using a tiled layout
*/
if (brw->gen >= 9 &&
(mt->target == GL_TEXTURE_1D ||
mt->target == GL_TEXTURE_1D_ARRAY)) {
GLenum base_format = _mesa_get_format_base_format(mt->format);
if (base_format != GL_DEPTH_COMPONENT &&
base_format != GL_DEPTH_STENCIL &&
base_format != GL_STENCIL_INDEX)
return true;
}
return false;
}
static void
brw_miptree_layout_texture_array(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
unsigned height = mt->physical_height0;
bool layout_1d = gen9_use_linear_1d_layout(brw, mt);
int physical_qpitch;
if (layout_1d)
gen9_miptree_layout_1d(mt);
else if (mt->array_layout == GEN6_HIZ_STENCIL)
brw_miptree_layout_gen6_hiz_stencil(mt);
else
brw_miptree_layout_2d(mt);
if (layout_1d) {
physical_qpitch = 1;
/* When using the horizontal layout the qpitch specifies the distance in
* pixels between array slices. The total_width is forced to be a
* multiple of the horizontal alignment in brw_miptree_layout_1d (in
* this case it's always 64). The vertical alignment is ignored.
*/
mt->qpitch = mt->total_width;
} else {
mt->qpitch = brw_miptree_get_vertical_slice_pitch(brw, mt, 0);
/* Unlike previous generations the qpitch is a multiple of the
* compressed block size on Gen9 so physical_qpitch matches mt->qpitch.
*/
physical_qpitch = (mt->compressed && brw->gen < 9 ? mt->qpitch / 4 :
mt->qpitch);
}
for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
unsigned img_height;
img_height = ALIGN_NPOT(height, mt->valign);
if (mt->compressed)
img_height /= mt->valign;
for (unsigned q = 0; q < mt->level[level].depth; q++) {
if (mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
intel_miptree_set_image_offset(mt, level, q, 0, q * img_height);
} else {
intel_miptree_set_image_offset(mt, level, q, 0, q * physical_qpitch);
}
}
height = minify(height, 1);
}
if (mt->array_layout == ALL_LOD_IN_EACH_SLICE)
mt->total_height = physical_qpitch * mt->physical_depth0;
align_cube(mt);
}
static void
brw_miptree_layout_texture_3d(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
mt->total_width = 0;
mt->total_height = 0;
unsigned ysum = 0;
unsigned bh, bw;
_mesa_get_format_block_size(mt->format, &bw, &bh);
for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
unsigned WL = MAX2(mt->physical_width0 >> level, 1);
unsigned HL = MAX2(mt->physical_height0 >> level, 1);
unsigned DL = MAX2(mt->physical_depth0 >> level, 1);
unsigned wL = ALIGN_NPOT(WL, mt->halign);
unsigned hL = ALIGN_NPOT(HL, mt->valign);
if (mt->target == GL_TEXTURE_CUBE_MAP)
DL = 6;
intel_miptree_set_level_info(mt, level, 0, 0, DL);
for (unsigned q = 0; q < DL; q++) {
unsigned x = (q % (1 << level)) * wL;
unsigned y = ysum + (q >> level) * hL;
intel_miptree_set_image_offset(mt, level, q, x / bw, y / bh);
mt->total_width = MAX2(mt->total_width, (x + wL) / bw);
mt->total_height = MAX2(mt->total_height, (y + hL) / bh);
}
ysum += ALIGN(DL, 1 << level) / (1 << level) * hL;
}
align_cube(mt);
}
/**
* \brief Helper function for intel_miptree_create().
*/
static enum isl_tiling
brw_miptree_choose_tiling(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
uint32_t layout_flags)
{
if (mt->format == MESA_FORMAT_S_UINT8) {
/* The stencil buffer is W tiled. However, we request from the kernel a
* non-tiled buffer because the GTT is incapable of W fencing.
*/
return ISL_TILING_LINEAR;
}
/* Do not support changing the tiling for miptrees with pre-allocated BOs. */
assert((layout_flags & MIPTREE_LAYOUT_FOR_BO) == 0);
/* Some usages may want only one type of tiling, like depth miptrees (Y
* tiled), or temporary BOs for uploading data once (linear).
*/
switch (layout_flags & MIPTREE_LAYOUT_TILING_ANY) {
case MIPTREE_LAYOUT_TILING_ANY:
break;
case MIPTREE_LAYOUT_TILING_Y:
return ISL_TILING_Y0;
case MIPTREE_LAYOUT_TILING_NONE:
return ISL_TILING_LINEAR;
}
if (mt->surf.samples > 1) {
/* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
* Surface"):
*
* [DevSNB+]: For multi-sample render targets, this field must be
* 1. MSRTs can only be tiled.
*
* Our usual reason for preferring X tiling (fast blits using the
* blitting engine) doesn't apply to MSAA, since we'll generally be
* downsampling or upsampling when blitting between the MSAA buffer
* and another buffer, and the blitting engine doesn't support that.
* So use Y tiling, since it makes better use of the cache.
*/
return ISL_TILING_Y0;
}
GLenum base_format = _mesa_get_format_base_format(mt->format);
if (base_format == GL_DEPTH_COMPONENT ||
base_format == GL_DEPTH_STENCIL_EXT)
return ISL_TILING_Y0;
/* 1D textures (and 1D array textures) don't get any benefit from tiling,
* in fact it leads to a less efficient use of memory space and bandwidth
* due to tile alignment.
*/
if (mt->logical_height0 == 1)
return ISL_TILING_LINEAR;
int minimum_pitch = mt->total_width * mt->cpp;
/* If the width is much smaller than a tile, don't bother tiling. */
if (minimum_pitch < 64)
return ISL_TILING_LINEAR;
if (ALIGN(minimum_pitch, 512) >= 32768) {
perf_debug("%dx%d miptree too large to blit, falling back to untiled",
mt->total_width, mt->total_height);
return ISL_TILING_LINEAR;
}
/* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
if (brw->gen < 6)
return ISL_TILING_X;
/* From the Sandybridge PRM, Volume 1, Part 2, page 32:
* "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
* or Linear."
* 128 bits per pixel translates to 16 bytes per pixel. This is necessary
* all the way back to 965, but is permitted on Gen7+.
*/
if (brw->gen < 7 && mt->cpp >= 16)
return ISL_TILING_X;
/* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
* messages), on p64, under the heading "Surface Vertical Alignment":
*
* This field must be set to VALIGN_4 for all tiled Y Render Target
* surfaces.
*
* So if the surface is renderable and uses a vertical alignment of 2,
* force it to be X tiled. This is somewhat conservative (it's possible
* that the client won't ever render to this surface), but it's difficult
* to know that ahead of time. And besides, since we use a vertical
* alignment of 4 as often as we can, this shouldn't happen very often.
*/
if (brw->gen == 7 && mt->valign == 2 &&
brw->mesa_format_supports_render[mt->format]) {
return ISL_TILING_X;
}
return ISL_TILING_Y0;
}
static void
intel_miptree_set_total_width_height(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
switch (mt->target) {
case GL_TEXTURE_CUBE_MAP:
if (brw->gen == 4) {
/* Gen4 stores cube maps as 3D textures. */
assert(mt->physical_depth0 == 6);
brw_miptree_layout_texture_3d(brw, mt);
} else {
/* All other hardware stores cube maps as 2D arrays. */
brw_miptree_layout_texture_array(brw, mt);
}
break;
case GL_TEXTURE_3D:
if (brw->gen >= 9)
brw_miptree_layout_texture_array(brw, mt);
else
brw_miptree_layout_texture_3d(brw, mt);
break;
case GL_TEXTURE_1D_ARRAY:
case GL_TEXTURE_2D_ARRAY:
case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
case GL_TEXTURE_CUBE_MAP_ARRAY:
brw_miptree_layout_texture_array(brw, mt);
break;
default:
switch (mt->surf.msaa_layout) {
case ISL_MSAA_LAYOUT_ARRAY:
brw_miptree_layout_texture_array(brw, mt);
break;
case ISL_MSAA_LAYOUT_NONE:
case ISL_MSAA_LAYOUT_INTERLEAVED:
if (gen9_use_linear_1d_layout(brw, mt))
gen9_miptree_layout_1d(mt);
else if (mt->array_layout == GEN6_HIZ_STENCIL)
brw_miptree_layout_gen6_hiz_stencil(mt);
else
brw_miptree_layout_2d(mt);
break;
}
break;
}
DBG("%s: %dx%dx%d\n", __func__,
mt->total_width, mt->total_height, mt->cpp);
}
static void
intel_miptree_set_alignment(struct brw_context *brw,
struct intel_mipmap_tree *mt,
uint32_t layout_flags)
{
/**
* From the "Alignment Unit Size" section of various specs, namely:
* - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
* - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
* - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
* - BSpec (for Ivybridge and slight variations in separate stencil)
*/
if (mt->array_layout == GEN6_HIZ_STENCIL) {
/* On gen6, we use GEN6_HIZ_STENCIL for stencil/hiz because the
* hardware doesn't support multiple mip levels on stencil/hiz.
*
* PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer:
* "The hierarchical depth buffer does not support the LOD field"
*
* PRM Vol 2, Part 1, 7.5.4.1 Separate Stencil Buffer:
* "The stencil depth buffer does not support the LOD field"
*/
if (mt->format == MESA_FORMAT_S_UINT8) {
/* Stencil uses W tiling, so we force W tiling alignment for the
* ALL_SLICES_AT_EACH_LOD miptree layout.
*/
mt->halign = 4;
mt->valign = 2;
assert((layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16) == 0);
} else {
/* See brw_miptree_layout_gen6_hiz_stencil() */
mt->halign = 1;
mt->valign = 2;
}
} else if (mt->compressed) {
/* The hardware alignment requirements for compressed textures
* happen to match the block boundaries.
*/
_mesa_get_format_block_size(mt->format, &mt->halign, &mt->valign);
/* On Gen9+ we can pick our own alignment for compressed textures but it
* has to be a multiple of the block size. The minimum alignment we can
* pick is 4 so we effectively have to align to 4 times the block
* size
*/
if (brw->gen >= 9) {
mt->halign *= 4;
mt->valign *= 4;
}
} else if (mt->format == MESA_FORMAT_S_UINT8) {
mt->halign = 8;
mt->valign = brw->gen >= 7 ? 8 : 4;
} else {
mt->halign =
intel_horizontal_texture_alignment_unit(brw, mt, layout_flags);
mt->valign = intel_vertical_texture_alignment_unit(brw, mt);
}
}
bool
brw_miptree_layout(struct brw_context *brw,
struct intel_mipmap_tree *mt,
uint32_t layout_flags)
{
intel_miptree_set_alignment(brw, mt, layout_flags);
intel_miptree_set_total_width_height(brw, mt);
if (!mt->total_width || !mt->total_height)
return false;
/* On Gen9+ the alignment values are expressed in multiples of the block
* size
*/
if (brw->gen >= 9) {
unsigned int i, j;
_mesa_get_format_block_size(mt->format, &i, &j);
mt->halign /= i;
mt->valign /= j;
}
if ((layout_flags & MIPTREE_LAYOUT_FOR_BO) == 0)
mt->surf.tiling = brw_miptree_choose_tiling(brw, mt, layout_flags);
return true;
}

23
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View File

@@ -80,15 +80,7 @@ get_isl_surf(struct brw_context *brw, struct intel_mipmap_tree *mt,
uint32_t *tile_x, uint32_t *tile_y,
uint32_t *offset, struct isl_surf *surf)
{
if (mt->surf.size > 0) {
*surf = mt->surf;
} else {
intel_miptree_get_isl_surf(brw, mt, surf);
surf->dim = get_isl_surf_dim(target);
}
assert(mt->array_layout != GEN6_HIZ_STENCIL);
*surf = mt->surf;
const enum isl_dim_layout dim_layout =
get_isl_dim_layout(&brw->screen->devinfo, mt->surf.tiling, target);
@@ -561,12 +553,10 @@ brw_update_texture_surface(struct gl_context *ctx,
unsigned view_num_layers;
if (obj->Immutable && obj->Target != GL_TEXTURE_3D) {
view_num_layers = obj->NumLayers;
} else if (mt->surf.size > 0) {
} else {
view_num_layers = mt->surf.dim == ISL_SURF_DIM_3D ?
mt->surf.logical_level0_px.depth :
mt->surf.logical_level0_px.array_len;
} else {
view_num_layers = mt->logical_depth0;
}
/* Handling GL_ALPHA as a surface format override breaks 1.30+ style
@@ -1663,14 +1653,9 @@ get_image_num_layers(const struct intel_mipmap_tree *mt, GLenum target,
if (target == GL_TEXTURE_CUBE_MAP)
return 6;
if (mt->surf.size > 0) {
return target == GL_TEXTURE_3D ?
minify(mt->surf.logical_level0_px.depth, level) :
mt->surf.logical_level0_px.array_len;
}
return target == GL_TEXTURE_3D ?
minify(mt->logical_depth0, level) : mt->logical_depth0;
minify(mt->surf.logical_level0_px.depth, level) :
mt->surf.logical_level0_px.array_len;
}
static void

8
src/mesa/drivers/dri/i965/gen6_depth_state.c
View File

@@ -91,8 +91,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
break;
case GL_TEXTURE_3D:
assert(mt);
depth = mt->surf.size > 0 ? mt->surf.logical_level0_px.depth :
MAX2(mt->logical_depth0, 1);
depth = mt->surf.logical_level0_px.depth;
/* fallthrough */
default:
surftype = translate_tex_target(gl_target);
@@ -103,12 +102,9 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
lod = irb ? irb->mt_level - irb->mt->first_level : 0;
if (mt && mt->surf.size > 0) {
if (mt) {
width = mt->surf.logical_level0_px.width;
height = mt->surf.logical_level0_px.height;
} else if (mt) {
width = mt->logical_width0;
height = mt->logical_height0;
}
BEGIN_BATCH(7);

8
src/mesa/drivers/dri/i965/gen7_misc_state.c
View File

@@ -83,8 +83,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
break;
case GL_TEXTURE_3D:
assert(mt);
depth = mt->surf.size > 0 ? mt->surf.logical_level0_px.depth :
MAX2(mt->logical_depth0, 1);
depth = mt->surf.logical_level0_px.depth;
/* fallthrough */
default:
surftype = translate_tex_target(gl_target);
@@ -95,12 +94,9 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
lod = irb ? irb->mt_level - irb->mt->first_level : 0;
if (mt && mt->surf.size > 0) {
if (mt) {
width = mt->surf.logical_level0_px.width;
height = mt->surf.logical_level0_px.height;
} else if (mt) {
width = mt->logical_width0;
height = mt->logical_height0;
}
/* _NEW_DEPTH, _NEW_STENCIL, _NEW_BUFFERS */

8
src/mesa/drivers/dri/i965/gen8_depth_state.c
View File

@@ -176,8 +176,7 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
break;
case GL_TEXTURE_3D:
assert(mt);
depth = mt->surf.size > 0 ? mt->surf.logical_level0_px.depth :
MAX2(mt->logical_depth0, 1);
depth = mt->surf.logical_level0_px.depth;
surftype = translate_tex_target(gl_target);
break;
case GL_TEXTURE_1D_ARRAY:
@@ -200,12 +199,9 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
lod = irb ? irb->mt_level - irb->mt->first_level : 0;
if (mt && mt->surf.size > 0) {
if (mt) {
width = mt->surf.logical_level0_px.width;
height = mt->surf.logical_level0_px.height;
} else if (mt) {
width = mt->logical_width0;
height = mt->logical_height0;
}
emit_depth_packets(brw, depth_mt, brw_depthbuffer_format(brw), surftype,

33
src/mesa/drivers/dri/i965/intel_blit.c
View File

@@ -171,12 +171,12 @@ get_blit_intratile_offset_el(const struct brw_context *brw,
uint32_t *x_offset_el,
uint32_t *y_offset_el)
{
enum isl_tiling tiling = intel_miptree_get_isl_tiling(mt);
isl_tiling_get_intratile_offset_el(tiling, mt->cpp * 8, mt->surf.row_pitch,
isl_tiling_get_intratile_offset_el(mt->surf.tiling,
mt->cpp * 8, mt->surf.row_pitch,
total_x_offset_el, total_y_offset_el,
base_address_offset,
x_offset_el, y_offset_el);
if (tiling == ISL_TILING_LINEAR) {
if (mt->surf.tiling == ISL_TILING_LINEAR) {
/* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress:
*
* "Base address of the destination surface: X=0, Y=0. Lower 32bits
@@ -329,14 +329,12 @@ intel_miptree_blit(struct brw_context *brw,
intel_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true);
if (src_flip) {
const unsigned h0 = src_mt->surf.size > 0 ?
src_mt->surf.phys_level0_sa.height : src_mt->physical_height0;
const unsigned h0 = src_mt->surf.phys_level0_sa.height;
src_y = minify(h0, src_level - src_mt->first_level) - src_y - height;
}
if (dst_flip) {
const unsigned h0 = dst_mt->surf.size > 0 ?
dst_mt->surf.phys_level0_sa.height : dst_mt->physical_height0;
const unsigned h0 = dst_mt->surf.phys_level0_sa.height;
dst_y = minify(h0, dst_level - dst_mt->first_level) - dst_y - height;
}
@@ -407,21 +405,12 @@ intel_miptree_copy(struct brw_context *brw,
assert(src_x % bw == 0);
assert(src_y % bh == 0);
if (src_mt->surf.size > 0) {
assert(src_width % bw == 0 ||
src_x + src_width ==
minify(src_mt->surf.logical_level0_px.width, src_level));
assert(src_height % bh == 0 ||
src_y + src_height ==
minify(src_mt->surf.logical_level0_px.height, src_level));
} else {
assert(src_width % bw == 0 ||
src_x + src_width ==
minify(src_mt->logical_width0, src_level));
assert(src_height % bh == 0 ||
src_y + src_height ==
minify(src_mt->logical_height0, src_level));
}
assert(src_width % bw == 0 ||
src_x + src_width ==
minify(src_mt->surf.logical_level0_px.width, src_level));
assert(src_height % bh == 0 ||
src_y + src_height ==
minify(src_mt->surf.logical_level0_px.height, src_level));
src_x /= (int)bw;
src_y /= (int)bh;

42
src/mesa/drivers/dri/i965/intel_fbo.c
View File

@@ -532,19 +532,14 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw,
irb->mt_level = level;
irb->mt_layer = layer;
const unsigned layer_multiplier =
mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY ? mt->surf.samples : 1;
if (!layered) {
irb->layer_count = 1;
} else if (mt->target != GL_TEXTURE_3D && image->TexObject->NumLayers > 0) {
irb->layer_count = image->TexObject->NumLayers;
} else if (mt->surf.size > 0) {
} else {
irb->layer_count = mt->surf.dim == ISL_SURF_DIM_3D ?
minify(mt->surf.logical_level0_px.depth, level) :
mt->surf.logical_level0_px.array_len;
} else {
irb->layer_count = mt->level[level].depth / layer_multiplier;
}
intel_miptree_reference(&irb->mt, mt);
@@ -660,32 +655,17 @@ intel_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
if (depth_mt && stencil_mt) {
if (brw->gen >= 6) {
unsigned d_width, d_height, d_depth;
unsigned s_width, s_height, s_depth;
const unsigned d_width = depth_mt->surf.phys_level0_sa.width;
const unsigned d_height = depth_mt->surf.phys_level0_sa.height;
const unsigned d_depth = depth_mt->surf.dim == ISL_SURF_DIM_3D ?
depth_mt->surf.phys_level0_sa.depth :
depth_mt->surf.phys_level0_sa.array_len;
if (depth_mt->surf.size > 0) {
d_width = depth_mt->surf.phys_level0_sa.width;
d_height = depth_mt->surf.phys_level0_sa.height;
d_depth = depth_mt->surf.dim == ISL_SURF_DIM_3D ?
depth_mt->surf.phys_level0_sa.depth :
depth_mt->surf.phys_level0_sa.array_len;
} else {
d_width = depth_mt->physical_width0;
d_height = depth_mt->physical_height0;
d_depth = depth_mt->physical_depth0;
}
if (stencil_mt->surf.size > 0) {
s_width = stencil_mt->surf.phys_level0_sa.width;
s_height = stencil_mt->surf.phys_level0_sa.height;
s_depth = stencil_mt->surf.dim == ISL_SURF_DIM_3D ?
stencil_mt->surf.phys_level0_sa.depth :
stencil_mt->surf.phys_level0_sa.array_len;
} else {
s_width = stencil_mt->physical_width0;
s_height = stencil_mt->physical_height0;
s_depth = stencil_mt->physical_depth0;
}
const unsigned s_width = stencil_mt->surf.phys_level0_sa.width;
const unsigned s_height = stencil_mt->surf.phys_level0_sa.height;
const unsigned s_depth = stencil_mt->surf.dim == ISL_SURF_DIM_3D ?
stencil_mt->surf.phys_level0_sa.depth :
stencil_mt->surf.phys_level0_sa.array_len;
/* For gen >= 6, we are using the lod/minimum-array-element fields
* and supporting layered rendering. This means that we must restrict

583
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
View File

@@ -97,29 +97,6 @@ is_mcs_supported(const struct brw_context *brw, mesa_format format,
}
}
/**
* Determine which MSAA layout should be used by the MSAA surface being
* created, based on the chip generation and the surface type.
*/
static enum isl_msaa_layout
compute_msaa_layout(struct brw_context *brw, mesa_format format,
uint32_t layout_flags)
{
/* Prior to Gen7, all MSAA surfaces used IMS layout. */
if (brw->gen < 7)
return ISL_MSAA_LAYOUT_INTERLEAVED;
/* In Gen7, IMS layout is only used for depth and stencil buffers. */
switch (_mesa_get_format_base_format(format)) {
case GL_DEPTH_COMPONENT:
case GL_STENCIL_INDEX:
case GL_DEPTH_STENCIL:
return ISL_MSAA_LAYOUT_INTERLEAVED;
default:
return ISL_MSAA_LAYOUT_ARRAY;
}
}
static bool
intel_tiling_supports_ccs(const struct brw_context *brw,
enum isl_tiling tiling)
@@ -344,222 +321,6 @@ needs_separate_stencil(const struct brw_context *brw,
intel_miptree_supports_hiz(brw, mt);
}
/**
* @param for_bo Indicates that the caller is
* intel_miptree_create_for_bo(). If true, then do not create
* \c stencil_mt.
*/
static struct intel_mipmap_tree *
intel_miptree_create_layout(struct brw_context *brw,
GLenum target,
mesa_format format,
GLuint first_level,
GLuint last_level,
GLuint width0,
GLuint height0,
GLuint depth0,
GLuint num_samples,
uint32_t layout_flags)
{
assert(num_samples > 0);
struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
if (!mt)
return NULL;
DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__,
_mesa_enum_to_string(target),
_mesa_get_format_name(format),
first_level, last_level, depth0, mt);
if (target == GL_TEXTURE_1D_ARRAY)
assert(height0 == 1);
mt->target = target;
mt->format = format;
mt->first_level = first_level;
mt->last_level = last_level;
mt->logical_width0 = width0;
mt->logical_height0 = height0;
mt->logical_depth0 = depth0;
mt->is_scanout = (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT) != 0;
mt->aux_usage = ISL_AUX_USAGE_NONE;
mt->supports_fast_clear = false;
mt->aux_state = NULL;
mt->cpp = _mesa_get_format_bytes(format);
mt->surf.samples = num_samples;
mt->compressed = _mesa_is_format_compressed(format);
mt->surf.msaa_layout = ISL_MSAA_LAYOUT_NONE;
mt->refcount = 1;
if (brw->gen == 6 && format == MESA_FORMAT_S_UINT8)
layout_flags |= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL;
int depth_multiply = 1;
if (num_samples > 1) {
/* Adjust width/height/depth for MSAA */
mt->surf.msaa_layout = compute_msaa_layout(brw, format, layout_flags);
if (mt->surf.msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) {
/* From the Ivybridge PRM, Volume 1, Part 1, page 108:
* "If the surface is multisampled and it is a depth or stencil
* surface or Multisampled Surface StorageFormat in SURFACE_STATE is
* MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
* proceeding:
*
* +----------------------------------------------------------------+
* | Num Multisamples | W_l = | H_l = |
* +----------------------------------------------------------------+
* | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
* | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
* | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
* | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
* +----------------------------------------------------------------+
* "
*
* Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
* format rather than UMS/CMS (array slices). The Sandybridge PRM,
* Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
*
* Another more complicated explanation for these adjustments comes
* from the Sandybridge PRM, volume 4, part 1, page 31:
*
* "Any of the other messages (sample*, LOD, load4) used with a
* (4x) multisampled surface will in-effect sample a surface with
* double the height and width as that indicated in the surface
* state. Each pixel position on the original-sized surface is
* replaced with a 2x2 of samples with the following arrangement:
*
* sample 0 sample 2
* sample 1 sample 3"
*
* Thus, when sampling from a multisampled texture, it behaves as
* though the layout in memory for (x,y,sample) is:
*
* (0,0,0) (0,0,2) (1,0,0) (1,0,2)
* (0,0,1) (0,0,3) (1,0,1) (1,0,3)
*
* (0,1,0) (0,1,2) (1,1,0) (1,1,2)
* (0,1,1) (0,1,3) (1,1,1) (1,1,3)
*
* However, the actual layout of multisampled data in memory is:
*
* (0,0,0) (1,0,0) (0,0,1) (1,0,1)
* (0,1,0) (1,1,0) (0,1,1) (1,1,1)
*
* (0,0,2) (1,0,2) (0,0,3) (1,0,3)
* (0,1,2) (1,1,2) (0,1,3) (1,1,3)
*
* This pattern repeats for each 2x2 pixel block.
*
* As a result, when calculating the size of our 4-sample buffer for
* an odd width or height, we have to align before scaling up because
* sample 3 is in that bottom right 2x2 block.
*/
switch (num_samples) {
case 2:
assert(brw->gen >= 8);
width0 = ALIGN(width0, 2) * 2;
height0 = ALIGN(height0, 2);
break;
case 4:
width0 = ALIGN(width0, 2) * 2;
height0 = ALIGN(height0, 2) * 2;
break;
case 8:
width0 = ALIGN(width0, 2) * 4;
height0 = ALIGN(height0, 2) * 2;
break;
case 16:
width0 = ALIGN(width0, 2) * 4;
height0 = ALIGN(height0, 2) * 4;
break;
default:
/* num_samples should already have been quantized to 0, 1, 2, 4, 8
* or 16.
*/
unreachable("not reached");
}
} else {
/* Non-interleaved */
depth_multiply = num_samples;
depth0 *= depth_multiply;
}
}
if (!create_mapping_table(target, first_level, last_level, depth0,
mt->level)) {
free(mt);
return NULL;
}
/* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
* be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
* Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
* used on Gen8 to make it pick a qpitch value which doesn't include space
* for the mipmaps. On Gen9 this is not necessary because it will
* automatically pick a packed qpitch value whenever mt->first_level ==
* mt->last_level.
* TODO: can we use it elsewhere?
* TODO: also disable this on Gen8 and pick the qpitch value like Gen9
*/
if (brw->gen >= 9) {
mt->array_layout = ALL_LOD_IN_EACH_SLICE;
} else {
switch (mt->surf.msaa_layout) {
case ISL_MSAA_LAYOUT_NONE:
case ISL_MSAA_LAYOUT_INTERLEAVED:
mt->array_layout = ALL_LOD_IN_EACH_SLICE;
break;
case ISL_MSAA_LAYOUT_ARRAY:
mt->array_layout = ALL_SLICES_AT_EACH_LOD;
break;
}
}
if (target == GL_TEXTURE_CUBE_MAP)
assert(depth0 == 6 * depth_multiply);
mt->physical_width0 = width0;
mt->physical_height0 = height0;
mt->physical_depth0 = depth0;
assert(!needs_separate_stencil(brw, mt, format, layout_flags));
/*
* Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
* multisampled or have an AUX buffer attached to it.
*
* GEN | MSRT | AUX_CCS_* or AUX_MCS
* -------------------------------------------
* 9 | HALIGN_16 | HALIGN_16
* 8 | HALIGN_ANY | HALIGN_16
* 7 | ? | ?
* 6 | ? | ?
*/
if (intel_miptree_supports_ccs(brw, mt)) {
if (brw->gen >= 9 || (brw->gen == 8 && num_samples == 1))
layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
} else if (brw->gen >= 9 && num_samples > 1) {
layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
} else {
const UNUSED bool is_lossless_compressed_aux =
brw->gen >= 9 && num_samples == 1 &&
mt->format == MESA_FORMAT_R_UINT32;
/* For now, nothing else has this requirement */
assert(is_lossless_compressed_aux ||
(layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16) == 0);
}
if (!brw_miptree_layout(brw, mt, layout_flags)) {
intel_miptree_release(&mt);
return NULL;
}
return mt;
}
/**
* Choose the aux usage for this miptree. This function must be called fairly
* late in the miptree create process after we have a tiling.
@@ -662,11 +423,7 @@ intel_miptree_check_level_layer(const struct intel_mipmap_tree *mt,
assert(level >= mt->first_level);
assert(level <= mt->last_level);
if (mt->surf.size > 0)
assert(layer < get_num_phys_layers(&mt->surf, level));
else
assert(layer < mt->level[level].depth);
assert(layer < get_num_phys_layers(&mt->surf, level));
}
static enum isl_aux_state **
@@ -676,12 +433,8 @@ create_aux_state_map(struct intel_mipmap_tree *mt,
const uint32_t levels = mt->last_level + 1;
uint32_t total_slices = 0;
for (uint32_t level = 0; level < levels; level++) {
if (mt->surf.size > 0)
total_slices += get_num_phys_layers(&mt->surf, level);
else
total_slices += mt->level[level].depth;
}
for (uint32_t level = 0; level < levels; level++)
total_slices += get_num_phys_layers(&mt->surf, level);
const size_t per_level_array_size = levels * sizeof(enum isl_aux_state *);
@@ -700,11 +453,7 @@ create_aux_state_map(struct intel_mipmap_tree *mt,
for (uint32_t level = 0; level < levels; level++) {
per_level_arr[level] = s;
unsigned level_depth;
if (mt->surf.size > 0)
level_depth = get_num_phys_layers(&mt->surf, level);
else
level_depth = mt->level[level].depth;
const unsigned level_depth = get_num_phys_layers(&mt->surf, level);
for (uint32_t a = 0; a < level_depth; a++)
*(s++) = initial;
@@ -1212,8 +961,6 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
mt->target = target;
mt->level[0].level_x = image->tile_x;
mt->level[0].level_y = image->tile_y;
mt->level[0].slice[0].x_offset = image->tile_x;
mt->level[0].slice[0].y_offset = image->tile_y;
/* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
* for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
@@ -1456,79 +1203,18 @@ intel_miptree_match_image(struct intel_mipmap_tree *mt,
if (mt->target == GL_TEXTURE_CUBE_MAP)
depth = 6;
if (mt->surf.size > 0) {
if (level >= mt->surf.levels)
return false;
const unsigned level_depth =
mt->surf.dim == ISL_SURF_DIM_3D ?
minify(mt->surf.logical_level0_px.depth, level) :
mt->surf.logical_level0_px.array_len;
return width == minify(mt->surf.logical_level0_px.width, level) &&
height == minify(mt->surf.logical_level0_px.height, level) &&
depth == level_depth &&
MAX2(image->NumSamples, 1) == mt->surf.samples;
}
int level_depth = mt->level[level].depth;
if (mt->surf.samples > 1 && mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY)
level_depth /= mt->surf.samples;
/* Test image dimensions against the base level image adjusted for
* minification. This will also catch images not present in the
* tree, changed targets, etc.
*/
if (width != minify(mt->logical_width0, level - mt->first_level) ||
height != minify(mt->logical_height0, level - mt->first_level) ||
depth != level_depth) {
return false;
}
/* Core uses sample number of zero to indicate single-sampled. */
if (MAX2(image->NumSamples, 1) != mt->surf.samples)
if (level >= mt->surf.levels)
return false;
return true;
}
const unsigned level_depth =
mt->surf.dim == ISL_SURF_DIM_3D ?
minify(mt->surf.logical_level0_px.depth, level) :
mt->surf.logical_level0_px.array_len;
void
intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
GLuint level,
GLuint x, GLuint y, GLuint d)
{
mt->level[level].depth = d;
mt->level[level].level_x = x;
mt->level[level].level_y = y;
DBG("%s level %d, depth %d, offset %d,%d\n", __func__,
level, d, x, y);
assert(mt->level[level].slice);
mt->level[level].slice[0].x_offset = mt->level[level].level_x;
mt->level[level].slice[0].y_offset = mt->level[level].level_y;
}
void
intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
GLuint level, GLuint img,
GLuint x, GLuint y)
{
if (img == 0 && level == 0)
assert(x == 0 && y == 0);
assert(img < mt->level[level].depth);
mt->level[level].slice[img].x_offset = mt->level[level].level_x + x;
mt->level[level].slice[img].y_offset = mt->level[level].level_y + y;
DBG("%s level %d img %d pos %d,%d\n",
__func__, level, img,
mt->level[level].slice[img].x_offset,
mt->level[level].slice[img].y_offset);
return width == minify(mt->surf.logical_level0_px.width, level) &&
height == minify(mt->surf.logical_level0_px.height, level) &&
depth == level_depth &&
MAX2(image->NumSamples, 1) == mt->surf.samples;
}
void
@@ -1542,36 +1228,28 @@ intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
return;
}
if (mt->surf.size > 0) {
uint32_t x_offset_sa, y_offset_sa;
uint32_t x_offset_sa, y_offset_sa;
/* Miptree itself can have an offset only if it represents a single
* slice in an imported buffer object.
* See intel_miptree_create_for_dri_image().
*/
assert(mt->level[0].level_x == 0);
assert(mt->level[0].level_y == 0);
/* Miptree itself can have an offset only if it represents a single
* slice in an imported buffer object.
* See intel_miptree_create_for_dri_image().
*/
assert(mt->level[0].level_x == 0);
assert(mt->level[0].level_y == 0);
/* Given level is relative to level zero while the miptree may be
* represent just a subset of all levels starting from 'first_level'.
*/
assert(level >= mt->first_level);
level -= mt->first_level;
/* Given level is relative to level zero while the miptree may be
* represent just a subset of all levels starting from 'first_level'.
*/
assert(level >= mt->first_level);
level -= mt->first_level;
const unsigned z = mt->surf.dim == ISL_SURF_DIM_3D ? slice : 0;
slice = mt->surf.dim == ISL_SURF_DIM_3D ? 0 : slice;
isl_surf_get_image_offset_el(&mt->surf, level, slice, z,
&x_offset_sa, &y_offset_sa);
const unsigned z = mt->surf.dim == ISL_SURF_DIM_3D ? slice : 0;
slice = mt->surf.dim == ISL_SURF_DIM_3D ? 0 : slice;
isl_surf_get_image_offset_el(&mt->surf, level, slice, z,
&x_offset_sa, &y_offset_sa);
*x = x_offset_sa;
*y = y_offset_sa;
return;
}
assert(slice < mt->level[level].depth);
*x = mt->level[level].slice[slice].x_offset;
*y = mt->level[level].slice[slice].y_offset;
*x = x_offset_sa;
*y = y_offset_sa;
}
@@ -1686,8 +1364,7 @@ intel_miptree_copy_slice_sw(struct brw_context *brw,
{
void *src, *dst;
ptrdiff_t src_stride, dst_stride;
const unsigned cpp = dst_mt->surf.size > 0 ?
(isl_format_get_layout(dst_mt->surf.format)->bpb / 8) : dst_mt->cpp;
const unsigned cpp = (isl_format_get_layout(dst_mt->surf.format)->bpb / 8);
intel_miptree_map(brw, src_mt,
src_level, src_layer,
@@ -1749,24 +1426,13 @@ intel_miptree_copy_slice(struct brw_context *brw,
{
mesa_format format = src_mt->format;
uint32_t width, height;
unsigned width = minify(src_mt->surf.phys_level0_sa.width,
src_level - src_mt->first_level);
unsigned height = minify(src_mt->surf.phys_level0_sa.height,
src_level - src_mt->first_level);
if (src_mt->surf.size > 0) {
width = minify(src_mt->surf.phys_level0_sa.width,
src_level - src_mt->first_level);
height = minify(src_mt->surf.phys_level0_sa.height,
src_level - src_mt->first_level);
assert(src_layer <
get_num_phys_layers(&src_mt->surf,
src_level - src_mt->first_level));
} else {
width = minify(src_mt->physical_width0,
src_level - src_mt->first_level);
height = minify(src_mt->physical_height0,
src_level - src_mt->first_level);
assert(src_layer < src_mt->level[src_level].depth);
}
assert(src_layer < get_num_phys_layers(&src_mt->surf,
src_level - src_mt->first_level));
assert(src_mt->format == dst_mt->format);
@@ -2200,8 +1866,7 @@ intel_miptree_has_color_unresolved(const struct intel_mipmap_tree *mt,
num_levels = last_level - start_level + 1;
for (uint32_t level = start_level; level <= last_level; level++) {
uint32_t level_layers = mt->surf.size > 0 ?
get_num_phys_layers(&mt->surf, level) : mt->level[level].depth;
uint32_t level_layers = get_num_phys_layers(&mt->surf, level);
level_layers = MIN2(num_layers, level_layers);
@@ -2542,12 +2207,7 @@ miptree_layer_range_length(const struct intel_mipmap_tree *mt, uint32_t level,
uint32_t start_layer, uint32_t num_layers)
{
assert(level <= mt->last_level);
uint32_t total_num_layers;
if (mt->surf.size > 0)
total_num_layers = get_num_phys_layers(&mt->surf, level);
else
total_num_layers = mt->level[level].depth;
const uint32_t total_num_layers = get_num_phys_layers(&mt->surf, level);
assert(start_layer < total_num_layers);
if (num_layers == INTEL_REMAINING_LAYERS)
@@ -2958,23 +2618,10 @@ intel_miptree_updownsample(struct brw_context *brw,
struct intel_mipmap_tree *src,
struct intel_mipmap_tree *dst)
{
unsigned src_w, src_h, dst_w, dst_h;
if (src->surf.size > 0) {
src_w = src->surf.logical_level0_px.width;
src_h = src->surf.logical_level0_px.height;
} else {
src_w = src->logical_width0;
src_h = src->logical_height0;
}
if (dst->surf.size > 0) {
dst_w = dst->surf.logical_level0_px.width;
dst_h = dst->surf.logical_level0_px.height;
} else {
dst_w = dst->logical_width0;
dst_h = dst->logical_height0;
}
unsigned src_w = src->surf.logical_level0_px.width;
unsigned src_h = src->surf.logical_level0_px.height;
unsigned dst_w = dst->surf.logical_level0_px.width;
unsigned dst_h = dst->surf.logical_level0_px.height;
brw_blorp_blit_miptrees(brw,
src, 0 /* level */, 0 /* layer */,
@@ -2986,21 +2633,10 @@ intel_miptree_updownsample(struct brw_context *brw,
false, false);
if (src->stencil_mt) {
if (src->stencil_mt->surf.size > 0) {
src_w = src->stencil_mt->surf.logical_level0_px.width;
src_h = src->stencil_mt->surf.logical_level0_px.height;
} else {
src_w = src->stencil_mt->logical_width0;
src_h = src->stencil_mt->logical_height0;
}
if (dst->stencil_mt->surf.size > 0) {
dst_w = dst->stencil_mt->surf.logical_level0_px.width;
dst_h = dst->stencil_mt->surf.logical_level0_px.height;
} else {
dst_w = dst->stencil_mt->logical_width0;
dst_h = dst->stencil_mt->logical_height0;
}
src_w = src->stencil_mt->surf.logical_level0_px.width;
src_h = src->stencil_mt->surf.logical_level0_px.height;
dst_w = dst->stencil_mt->surf.logical_level0_px.width;
dst_h = dst->stencil_mt->surf.logical_level0_px.height;
brw_blorp_blit_miptrees(brw,
src->stencil_mt, 0 /* level */, 0 /* layer */,
@@ -3798,129 +3434,6 @@ get_isl_dim_layout(const struct gen_device_info *devinfo,
unreachable("Invalid texture target");
}
enum isl_tiling
intel_miptree_get_isl_tiling(const struct intel_mipmap_tree *mt)
{
if (mt->format == MESA_FORMAT_S_UINT8)
return ISL_TILING_W;
return mt->surf.tiling;
}
void
intel_miptree_get_isl_surf(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
struct isl_surf *surf)
{
assert(mt->array_layout != GEN6_HIZ_STENCIL);
surf->dim = get_isl_surf_dim(mt->target);
surf->dim_layout = get_isl_dim_layout(&brw->screen->devinfo,
mt->surf.tiling, mt->target);
surf->msaa_layout = mt->surf.msaa_layout;
surf->tiling = intel_miptree_get_isl_tiling(mt);
surf->row_pitch = mt->surf.row_pitch;
surf->format = translate_tex_format(brw, mt->format, false);
if (brw->gen >= 9) {
if (surf->dim == ISL_SURF_DIM_1D && surf->tiling == ISL_TILING_LINEAR) {
/* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
surf->image_alignment_el = isl_extent3d(64, 1, 1);
} else {
/* On gen9+, intel_mipmap_tree stores the horizontal and vertical
* alignment in terms of surface elements like we want.
*/
surf->image_alignment_el = isl_extent3d(mt->halign, mt->valign, 1);
}
} else {
/* On earlier gens it's stored in pixels. */
unsigned bw, bh;
_mesa_get_format_block_size(mt->format, &bw, &bh);
surf->image_alignment_el =
isl_extent3d(mt->halign / bw, mt->valign / bh, 1);
}
surf->logical_level0_px.width = mt->logical_width0;
surf->logical_level0_px.height = mt->logical_height0;
if (surf->dim == ISL_SURF_DIM_3D) {
surf->logical_level0_px.depth = mt->logical_depth0;
surf->logical_level0_px.array_len = 1;
} else {
surf->logical_level0_px.depth = 1;
surf->logical_level0_px.array_len = mt->logical_depth0;
}
surf->phys_level0_sa.width = mt->physical_width0;
surf->phys_level0_sa.height = mt->physical_height0;
if (surf->dim == ISL_SURF_DIM_3D) {
surf->phys_level0_sa.depth = mt->physical_depth0;
surf->phys_level0_sa.array_len = 1;
} else {
surf->phys_level0_sa.depth = 1;
surf->phys_level0_sa.array_len = mt->physical_depth0;
}
surf->levels = mt->last_level - mt->first_level + 1;
surf->samples = mt->surf.samples;
surf->size = 0; /* TODO */
surf->alignment = 0; /* TODO */
switch (surf->dim_layout) {
case ISL_DIM_LAYOUT_GEN4_2D:
case ISL_DIM_LAYOUT_GEN4_3D:
case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ:
if (brw->gen >= 9) {
surf->array_pitch_el_rows = mt->qpitch;
} else {
unsigned bw, bh;
_mesa_get_format_block_size(mt->format, &bw, &bh);
assert(mt->qpitch % bh == 0);
surf->array_pitch_el_rows = mt->qpitch / bh;
}
break;
case ISL_DIM_LAYOUT_GEN9_1D:
surf->array_pitch_el_rows = 1;
break;
}
switch (mt->array_layout) {
case ALL_LOD_IN_EACH_SLICE:
surf->array_pitch_span = ISL_ARRAY_PITCH_SPAN_FULL;
break;
case ALL_SLICES_AT_EACH_LOD:
case GEN6_HIZ_STENCIL:
surf->array_pitch_span = ISL_ARRAY_PITCH_SPAN_COMPACT;
break;
default:
unreachable("Invalid array layout");
}
GLenum base_format = _mesa_get_format_base_format(mt->format);
switch (base_format) {
case GL_DEPTH_COMPONENT:
surf->usage = ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_TEXTURE_BIT;
break;
case GL_STENCIL_INDEX:
surf->usage = ISL_SURF_USAGE_STENCIL_BIT;
if (brw->gen >= 8)
surf->usage |= ISL_SURF_USAGE_TEXTURE_BIT;
break;
case GL_DEPTH_STENCIL:
/* In this case we only texture from the depth part */
surf->usage = ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT |
ISL_SURF_USAGE_TEXTURE_BIT;
break;
default:
surf->usage = ISL_SURF_USAGE_TEXTURE_BIT;
if (brw->mesa_format_supports_render[mt->format])
surf->usage = ISL_SURF_USAGE_RENDER_TARGET_BIT;
break;
}
if (_mesa_is_cube_map_texture(mt->target))
surf->usage |= ISL_SURF_USAGE_CUBE_BIT;
}
enum isl_aux_usage
intel_miptree_get_aux_isl_usage(const struct brw_context *brw,
const struct intel_mipmap_tree *mt)

241
src/mesa/drivers/dri/i965/intel_mipmap_tree.h
View File

@@ -99,21 +99,6 @@ struct intel_mipmap_level
/** Offset to this miptree level, used in computing y_offset. */
GLuint level_y;
/**
* \brief Number of 2D slices in this miplevel.
*
* The exact semantics of depth varies according to the texture target:
* - For GL_TEXTURE_CUBE_MAP, depth is 6.
* - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
* identical for all miplevels in the texture.
* - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
* value, like width and height, varies with miplevel.
* - For other texture types, depth is 1.
* - Additionally, for UMS and CMS miptrees, depth is multiplied by
* sample count.
*/
GLuint depth;
/**
* \brief Is HiZ enabled for this level?
*
@@ -130,26 +115,6 @@ struct intel_mipmap_level
* layers in a 3D texture. The list's length is \c depth.
*/
struct intel_mipmap_slice {
/**
* \name Offset to slice
* \{
*
* Hardware formats are so diverse that that there is no unified way to
* compute the slice offsets, so we store them in this table.
*
* The (x, y) offset to slice \c s at level \c l relative the miptrees
* base address is
* \code
* x = mt->level[l].slice[s].x_offset
* y = mt->level[l].slice[s].y_offset
*
* On some hardware generations, we program these offsets into
* RENDER_SURFACE_STATE.XOffset and RENDER_SURFACE_STATE.YOffset.
*/
GLuint x_offset;
GLuint y_offset;
/** \} */
/**
* Mapping information. Persistent for the duration of
* intel_miptree_map/unmap on this slice.
@@ -158,93 +123,6 @@ struct intel_mipmap_level
} *slice;
};
enum miptree_array_layout {
/* Each array slice contains all miplevels packed together.
*
* Gen hardware usually wants multilevel miptrees configured this way.
*
* A 2D Array texture with 2 slices and multiple LODs using
* ALL_LOD_IN_EACH_SLICE would look somewhat like this:
*
* +----------+
* | |
* | |
* +----------+
* +---+ +-+
* | | +-+
* +---+ *
* +----------+
* | |
* | |
* +----------+
* +---+ +-+
* | | +-+
* +---+ *
*/
ALL_LOD_IN_EACH_SLICE,
/* Each LOD contains all slices of that LOD packed together.
*
* In some situations, Gen7+ hardware can use the array_spacing_lod0
* feature to save space when the surface only contains LOD 0.
*
* Gen6 uses this for separate stencil and hiz since gen6 does not support
* multiple LODs for separate stencil and hiz.
*
* A 2D Array texture with 2 slices and multiple LODs using
* ALL_SLICES_AT_EACH_LOD would look somewhat like this:
*
* +----------+
* | |
* | |
* +----------+
* | |
* | |
* +----------+
* +---+ +-+
* | | +-+
* +---+ +-+
* | | :
* +---+
*/
ALL_SLICES_AT_EACH_LOD,
/* On Sandy Bridge, HiZ and stencil buffers work the same as on Ivy Bridge
* except that they don't technically support mipmapping. That does not,
* however, stop us from doing it. As far as Sandy Bridge hardware is
* concerned, HiZ and stencil always operates on a single miplevel 2D
* (possibly array) image. The dimensions of that image are NOT minified.
*
* In order to implement HiZ and stencil on Sandy Bridge, we create one
* full-sized 2D (possibly array) image for every LOD with every image
* aligned to a page boundary. In order to save memory, we pretend that
* the width of each miplevel is minified and we place LOD1 and above below
* LOD0 but horizontally adjacent to each other. When considered as
* full-sized images, LOD1 and above technically overlap. However, since
* we only write to part of that image, the hardware will never notice the
* overlap.
*
* This layout looks something like this:
*
* +---------+
* | |
* | |
* +---------+
* | |
* | |
* +---------+
*
* +----+ +-+ .
* | | +-+
* +----+
*
* +----+ +-+ .
* | | +-+
* +----+
*/
GEN6_HIZ_STENCIL,
};
/**
* Miptree aux buffer. These buffers are associated with a miptree, but the
* format is managed by the hardware.
@@ -354,108 +232,14 @@ struct intel_mipmap_tree
*/
mesa_format etc_format;
/**
* @name Surface Alignment
* @{
*
* This defines the alignment of the upperleft pixel of each "slice" in the
* surface. The alignment is in pixel coordinates relative to the surface's
* most upperleft pixel, which is the pixel at (x=0, y=0, layer=0,
* level=0).
*
* The hardware docs do not use the term "slice". We use "slice" to mean
* the pixels at a given miplevel and layer. For 2D surfaces, the layer is
* the array slice; for 3D surfaces, the layer is the z offset.
*
* In the surface layout equations found in the hardware docs, the
* horizontal and vertical surface alignments often appear as variables 'i'
* and 'j'.
*/
/** @see RENDER_SURFACE_STATE.SurfaceHorizontalAlignment */
uint32_t halign;
/** @see RENDER_SURFACE_STATE.SurfaceVerticalAlignment */
uint32_t valign;
/** @} */
GLuint first_level;
GLuint last_level;
/**
* Level zero image dimensions. These dimensions correspond to the
* physical layout of data in memory. Accordingly, they account for the
* extra width, height, and or depth that must be allocated in order to
* accommodate multisample formats, and they account for the extra factor
* of 6 in depth that must be allocated in order to accommodate cubemap
* textures.
*/
GLuint physical_width0, physical_height0, physical_depth0;
/** Bytes per pixel (or bytes per block if compressed) */
GLuint cpp;
bool compressed;
/**
* @name Level zero image dimensions
* @{
*
* These dimensions correspond to the
* logical width, height, and depth of the texture as seen by client code.
* Accordingly, they do not account for the extra width, height, and/or
* depth that must be allocated in order to accommodate multisample
* formats, nor do they account for the extra factor of 6 in depth that
* must be allocated in order to accommodate cubemap textures.
*/
/**
* @see RENDER_SURFACE_STATE.Width
* @see 3DSTATE_DEPTH_BUFFER.Width
*/
uint32_t logical_width0;
/**
* @see RENDER_SURFACE_STATE.Height
* @see 3DSTATE_DEPTH_BUFFER.Height
*/
uint32_t logical_height0;
/**
* @see RENDER_SURFACE_STATE.Depth
* @see 3DSTATE_DEPTH_BUFFER.Depth
*/
uint32_t logical_depth0;
/** @} */
/**
* Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
* or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
*/
enum miptree_array_layout array_layout;
/**
* The distance in between array slices.
*
* The value is the one that is sent in the surface state. The actual
* meaning depends on certain criteria. Usually it is simply the number of
* uncompressed rows between each slice. However on Gen9+ for compressed
* surfaces it is the number of blocks. For 1D array surfaces that have the
* mipmap tree stored horizontally it is the number of pixels between each
* slice.
*
* @see RENDER_SURFACE_STATE.SurfaceQPitch
* @see 3DSTATE_DEPTH_BUFFER.SurfaceQPitch
* @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
* @see 3DSTATE_STENCIL_BUFFER.SurfaceQPitch
*/
uint32_t qpitch;
/* Derived from the above:
*/
GLuint total_width;
GLuint total_height;
/* Includes image offset tables: */
struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
@@ -670,14 +454,6 @@ enum isl_dim_layout
get_isl_dim_layout(const struct gen_device_info *devinfo,
enum isl_tiling tiling, GLenum target);
enum isl_tiling
intel_miptree_get_isl_tiling(const struct intel_mipmap_tree *mt);
void
intel_miptree_get_isl_surf(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
struct isl_surf *surf);
enum isl_aux_usage
intel_miptree_get_aux_isl_usage(const struct brw_context *brw,
const struct intel_mipmap_tree *mt);
@@ -703,14 +479,6 @@ uint32_t
intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
uint32_t x, uint32_t y);
void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
GLuint level,
GLuint x, GLuint y, GLuint d);
void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
GLuint level,
GLuint img, GLuint x, GLuint y);
void
intel_miptree_copy_slice(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
@@ -893,15 +661,6 @@ void
intel_update_r8stencil(struct brw_context *brw,
struct intel_mipmap_tree *mt);
/**
* Horizontal distance from one slice to the next in the two-dimensional
* miptree layout.
*/
unsigned
brw_miptree_get_horizontal_slice_pitch(const struct brw_context *brw,
const struct intel_mipmap_tree *mt,
unsigned level);
bool
brw_miptree_layout(struct brw_context *brw,
struct intel_mipmap_tree *mt,

13
src/mesa/drivers/dri/i965/intel_screen.c
View File

@@ -410,15 +410,10 @@ intel_setup_image_from_mipmap_tree(struct brw_context *brw, __DRIimage *image,
intel_miptree_check_level_layer(mt, level, zoffset);
if (mt->surf.size > 0) {
image->width = minify(mt->surf.phys_level0_sa.width,
level - mt->first_level);
image->height = minify(mt->surf.phys_level0_sa.height,
level - mt->first_level);
} else {
image->width = minify(mt->physical_width0, level - mt->first_level);
image->height = minify(mt->physical_height0, level - mt->first_level);
}
image->width = minify(mt->surf.phys_level0_sa.width,
level - mt->first_level);
image->height = minify(mt->surf.phys_level0_sa.height,
level - mt->first_level);
image->pitch = mt->surf.row_pitch;
image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset,

29
src/mesa/drivers/dri/i965/intel_tex_image.c
View File

@@ -62,16 +62,12 @@ intel_miptree_create_for_teximage(struct brw_context *brw,
intel_get_image_dims(&intelImage->base.Base, &width, &height, &depth);
if (old_mt && old_mt->surf.size > 0) {
if (old_mt) {
old_width = old_mt->surf.logical_level0_px.width;
old_height = old_mt->surf.logical_level0_px.height;
old_depth = old_mt->surf.dim == ISL_SURF_DIM_3D ?
old_mt->surf.logical_level0_px.depth :
old_mt->surf.logical_level0_px.array_len;
} else if (old_mt) {
old_width = old_mt->logical_width0;
old_height = old_mt->logical_height0;
old_depth = old_mt->logical_depth0;
}
DBG("%s\n", __func__);
@@ -198,16 +194,10 @@ intel_set_texture_image_mt(struct brw_context *brw,
struct intel_texture_object *intel_texobj = intel_texture_object(texobj);
struct intel_texture_image *intel_image = intel_texture_image(image);
if (mt->surf.size > 0) {
_mesa_init_teximage_fields(&brw->ctx, image,
mt->surf.logical_level0_px.width,
mt->surf.logical_level0_px.height, 1,
0, internal_format, mt->format);
} else {
_mesa_init_teximage_fields(&brw->ctx, image,
mt->logical_width0, mt->logical_height0, 1,
0, internal_format, mt->format);
}
_mesa_init_teximage_fields(&brw->ctx, image,
mt->surf.logical_level0_px.width,
mt->surf.logical_level0_px.height, 1,
0, internal_format, mt->format);
brw->ctx.Driver.FreeTextureImageBuffer(&brw->ctx, image);
@@ -462,12 +452,9 @@ intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx,
/* Since we are going to write raw data to the miptree, we need to resolve
* any pending fast color clears before we start.
*/
if (image->mt->surf.size > 0) {
assert(image->mt->surf.logical_level0_px.depth == 1);
assert(image->mt->surf.logical_level0_px.array_len == 1);
} else {
assert(image->mt->logical_depth0 == 1);
}
assert(image->mt->surf.logical_level0_px.depth == 1);
assert(image->mt->surf.logical_level0_px.array_len == 1);
intel_miptree_access_raw(brw, image->mt, level, 0, true);
bo = image->mt->bo;

8
src/mesa/drivers/dri/i965/intel_tex_subimage.c
View File

@@ -150,12 +150,8 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
/* Since we are going to write raw data to the miptree, we need to resolve
* any pending fast color clears before we start.
*/
if (image->mt->surf.size > 0) {
assert(image->mt->surf.logical_level0_px.depth == 1);
assert(image->mt->surf.logical_level0_px.array_len == 1);
} else {
assert(image->mt->logical_depth0 == 1);
}
assert(image->mt->surf.logical_level0_px.depth == 1);
assert(image->mt->surf.logical_level0_px.array_len == 1);
intel_miptree_access_raw(brw, image->mt, level, 0, true);