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intel/compiler: fine-grained control of dispatch widths

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Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20535>
This commit is contained in:
Marcin Ślusarz
2023-01-05 15:39:28 +01:00
committed by Marge Bot
parent bf3112805c
commit bed18ab3e2
7 changed files with 189 additions and 14 deletions
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15
src/intel/compiler/brw_compiler.c
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@@ -225,14 +225,29 @@ uint64_t
brw_get_compiler_config_value(const struct brw_compiler *compiler)
{
uint64_t config = 0;
unsigned bits = 0;
insert_u64_bit(&config, compiler->precise_trig);
bits++;
uint64_t mask = DEBUG_DISK_CACHE_MASK;
bits += util_bitcount64(mask);
while (mask != 0) {
const uint64_t bit = 1ULL << (ffsll(mask) - 1);
insert_u64_bit(&config, INTEL_DEBUG(bit));
mask &= ~bit;
}
mask = SIMD_DISK_CACHE_MASK;
bits += util_bitcount64(mask);
while (mask != 0) {
const uint64_t bit = 1ULL << (ffsll(mask) - 1);
insert_u64_bit(&config, (intel_simd & bit) != 0);
mask &= ~bit;
}
assert(bits <= util_bitcount64(UINT64_MAX));
return config;
}