intel/compiler: fine-grained control of dispatch widths

Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20535>

src/intel/compiler/brw_compiler.c

@@ -225,14 +225,29 @@ uint64_t
 brw_get_compiler_config_value(const struct brw_compiler *compiler)
 {
    uint64_t config = 0;
+   unsigned bits = 0;
+
    insert_u64_bit(&config, compiler->precise_trig);
+   bits++;
 
    uint64_t mask = DEBUG_DISK_CACHE_MASK;
+   bits += util_bitcount64(mask);
    while (mask != 0) {
       const uint64_t bit = 1ULL << (ffsll(mask) - 1);
       insert_u64_bit(&config, INTEL_DEBUG(bit));
       mask &= ~bit;
    }
+
+   mask = SIMD_DISK_CACHE_MASK;
+   bits += util_bitcount64(mask);
+   while (mask != 0) {
+      const uint64_t bit = 1ULL << (ffsll(mask) - 1);
+      insert_u64_bit(&config, (intel_simd & bit) != 0);
+      mask &= ~bit;
+   }
+
+   assert(bits <= util_bitcount64(UINT64_MAX));
+
    return config;
 }
 

src/intel/compiler/brw_fs.cpp

@@ -7551,7 +7551,7 @@ brw_compile_fs(const struct brw_compiler *compiler,
    if (!v8->run_fs(allow_spilling, false /* do_rep_send */)) {
       params->error_str = ralloc_strdup(mem_ctx, v8->fail_msg);
       return NULL;
-   } else if (!INTEL_DEBUG(DEBUG_NO8)) {
+   } else if (INTEL_SIMD(FS, 8)) {
       simd8_cfg = v8->cfg;
       prog_data->base.dispatch_grf_start_reg = v8->payload().num_regs;
       prog_data->reg_blocks_8 = brw_register_blocks(v8->grf_used);
@@ -7565,7 +7565,7 @@ brw_compile_fs(const struct brw_compiler *compiler,
     * See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/1917
     */
    if (devinfo->ver == 8 && prog_data->dual_src_blend &&
-       !INTEL_DEBUG(DEBUG_NO8)) {
+       INTEL_SIMD(FS, 8)) {
       assert(!params->use_rep_send);
       v8->limit_dispatch_width(8, "gfx8 workaround: "
                                "using SIMD8 when dual src blending.\n");
@@ -7585,7 +7585,7 @@ brw_compile_fs(const struct brw_compiler *compiler,
 
    if (!has_spilled &&
        v8->max_dispatch_width >= 16 &&
-       (!INTEL_DEBUG(DEBUG_NO16) || params->use_rep_send)) {
+       (INTEL_SIMD(FS, 16) || params->use_rep_send)) {
       /* Try a SIMD16 compile */
       v16 = std::make_unique<fs_visitor>(compiler, params->log_data, mem_ctx, &key->base,
                                          &prog_data->base, nir, 16,
@@ -7612,7 +7612,7 @@ brw_compile_fs(const struct brw_compiler *compiler,
    if (!has_spilled &&
        v8->max_dispatch_width >= 32 && !params->use_rep_send &&
        devinfo->ver >= 6 && !simd16_failed &&
-       !INTEL_DEBUG(DEBUG_NO32)) {
+       INTEL_SIMD(FS, 32)) {
       /* Try a SIMD32 compile */
       v32 = std::make_unique<fs_visitor>(compiler, params->log_data, mem_ctx, &key->base,
                                          &prog_data->base, nir, 32,

src/intel/compiler/brw_simd_selection.cpp

@@ -138,10 +138,33 @@ brw_simd_should_compile(brw_simd_selection_state &state, unsigned simd)
       return false;
    }
 
-   static const bool env_skip[] = {
-      INTEL_DEBUG(DEBUG_NO8) != 0,
-      INTEL_DEBUG(DEBUG_NO16) != 0,
-      INTEL_DEBUG(DEBUG_NO32) != 0,
+   uint64_t start;
+   switch (cs_prog_data->base.stage) {
+   case MESA_SHADER_COMPUTE:
+      start = DEBUG_CS_SIMD8;
+      break;
+   case MESA_SHADER_TASK:
+      start = DEBUG_TS_SIMD8;
+      break;
+   case MESA_SHADER_MESH:
+      start = DEBUG_MS_SIMD8;
+      break;
+   case MESA_SHADER_RAYGEN:
+   case MESA_SHADER_ANY_HIT:
+   case MESA_SHADER_CLOSEST_HIT:
+   case MESA_SHADER_MISS:
+   case MESA_SHADER_INTERSECTION:
+   case MESA_SHADER_CALLABLE:
+      start = DEBUG_RT_SIMD8;
+      break;
+   default:
+      unreachable(!"unknown shader stage in brw_simd_should_compile");
+   }
+
+   const bool env_skip[] = {
+      (intel_simd & (start << 0)) == 0,
+      (intel_simd & (start << 1)) == 0,
+      (intel_simd & (start << 2)) == 0,
    };
 
    static_assert(ARRAY_SIZE(env_skip) == SIMD_COUNT);

src/intel/compiler/test_simd_selection.cpp

@@ -51,6 +51,7 @@ protected:
       .prog_data = prog_data,
      }
    {
+      brw_process_intel_debug_variable();
    }
 
    ~SIMDSelectionTest() {