radeonsi: move si_nir_build_llvm into si_shader_llvm.c
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
This commit is contained in:
@@ -25,6 +25,7 @@
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#include "si_shader_internal.h"
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#include "si_pipe.h"
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#include "ac_rtld.h"
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#include "ac_nir_to_llvm.h"
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#include "sid.h"
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#include "tgsi/tgsi_from_mesa.h"
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@@ -363,3 +364,62 @@ void si_init_exec_from_input(struct si_shader_context *ctx, struct ac_arg param,
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"llvm.amdgcn.init.exec.from.input",
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ctx->ac.voidt, args, 2, AC_FUNC_ATTR_CONVERGENT);
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}
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bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
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{
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if (nir->info.stage == MESA_SHADER_VERTEX) {
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si_llvm_load_vs_inputs(ctx, nir);
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} else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
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unsigned colors_read =
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ctx->shader->selector->info.colors_read;
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LLVMValueRef main_fn = ctx->main_fn;
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LLVMValueRef undef = LLVMGetUndef(ctx->ac.f32);
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unsigned offset = SI_PARAM_POS_FIXED_PT + 1;
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if (colors_read & 0x0f) {
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unsigned mask = colors_read & 0x0f;
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LLVMValueRef values[4];
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values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
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values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
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values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
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values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
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ctx->abi.color0 =
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ac_to_integer(&ctx->ac,
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ac_build_gather_values(&ctx->ac, values, 4));
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}
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if (colors_read & 0xf0) {
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unsigned mask = (colors_read & 0xf0) >> 4;
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LLVMValueRef values[4];
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values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
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values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
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values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
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values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
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ctx->abi.color1 =
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ac_to_integer(&ctx->ac,
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ac_build_gather_values(&ctx->ac, values, 4));
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}
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ctx->abi.interp_at_sample_force_center =
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ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center;
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} else if (nir->info.stage == MESA_SHADER_COMPUTE) {
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if (nir->info.cs.user_data_components_amd) {
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ctx->abi.user_data = ac_get_arg(&ctx->ac, ctx->cs_user_data);
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ctx->abi.user_data = ac_build_expand_to_vec4(&ctx->ac, ctx->abi.user_data,
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nir->info.cs.user_data_components_amd);
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}
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}
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ctx->abi.inputs = &ctx->inputs[0];
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ctx->abi.clamp_shadow_reference = true;
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ctx->abi.robust_buffer_access = true;
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if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
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assert(gl_shader_stage_is_compute(nir->info.stage));
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si_declare_compute_memory(ctx);
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}
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ac_nir_translate(&ctx->ac, &ctx->abi, &ctx->args, nir);
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return true;
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}
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@@ -996,62 +996,3 @@ void si_finalize_nir(struct pipe_screen *screen, void *nirptr, bool optimize)
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si_nir_lower_ps_inputs(nir);
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si_lower_nir(sscreen, nir);
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}
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bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
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{
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if (nir->info.stage == MESA_SHADER_VERTEX) {
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si_llvm_load_vs_inputs(ctx, nir);
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} else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
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unsigned colors_read =
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ctx->shader->selector->info.colors_read;
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LLVMValueRef main_fn = ctx->main_fn;
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LLVMValueRef undef = LLVMGetUndef(ctx->ac.f32);
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unsigned offset = SI_PARAM_POS_FIXED_PT + 1;
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if (colors_read & 0x0f) {
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unsigned mask = colors_read & 0x0f;
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LLVMValueRef values[4];
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values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
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values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
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values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
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values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
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ctx->abi.color0 =
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ac_to_integer(&ctx->ac,
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ac_build_gather_values(&ctx->ac, values, 4));
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}
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if (colors_read & 0xf0) {
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unsigned mask = (colors_read & 0xf0) >> 4;
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LLVMValueRef values[4];
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values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
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values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
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values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
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values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
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ctx->abi.color1 =
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ac_to_integer(&ctx->ac,
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ac_build_gather_values(&ctx->ac, values, 4));
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}
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ctx->abi.interp_at_sample_force_center =
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ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center;
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} else if (nir->info.stage == MESA_SHADER_COMPUTE) {
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if (nir->info.cs.user_data_components_amd) {
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ctx->abi.user_data = ac_get_arg(&ctx->ac, ctx->cs_user_data);
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ctx->abi.user_data = ac_build_expand_to_vec4(&ctx->ac, ctx->abi.user_data,
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nir->info.cs.user_data_components_amd);
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}
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}
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ctx->abi.inputs = &ctx->inputs[0];
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ctx->abi.clamp_shadow_reference = true;
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ctx->abi.robust_buffer_access = true;
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if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
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assert(gl_shader_stage_is_compute(nir->info.stage));
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si_declare_compute_memory(ctx);
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}
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ac_nir_translate(&ctx->ac, &ctx->abi, &ctx->args, nir);
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return true;
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}
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