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radv: do not set registers for PSO states that are dynamic

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Dynamic states are emitted from the cmdbuf, setting them from the
pipeline has no effects because they should be ignored anyways.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17677>
This commit is contained in:
Samuel Pitoiset
2022-07-21 10:35:53 +02:00
committed by Marge Bot
parent 42803c70ef
commit bea050345e
3 changed files with 10 additions and 45 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -1454,8 +1454,7 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS |
RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_RESTART_ENABLE; RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_RESTART_ENABLE;
if (!cmd_buffer->state.emitted_graphics_pipeline || if (!cmd_buffer->state.emitted_graphics_pipeline)
cmd_buffer->state.emitted_graphics_pipeline->db_depth_control != pipeline->db_depth_control)
cmd_buffer->state.dirty |= cmd_buffer->state.dirty |=
RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE | RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE | RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE | RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP | RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE | RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP | RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE |
@@ -1720,28 +1719,17 @@ radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer)
static void static void
radv_emit_depth_control(struct radv_cmd_buffer *cmd_buffer) radv_emit_depth_control(struct radv_cmd_buffer *cmd_buffer)
{ {
unsigned db_depth_control = cmd_buffer->state.graphics_pipeline->db_depth_control;
struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
db_depth_control &= C_028800_Z_ENABLE & radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL,
C_028800_Z_WRITE_ENABLE & S_028800_Z_ENABLE(d->depth_test_enable ? 1 : 0) |
C_028800_ZFUNC & S_028800_Z_WRITE_ENABLE(d->depth_write_enable ? 1 : 0) |
C_028800_DEPTH_BOUNDS_ENABLE & S_028800_ZFUNC(d->depth_compare_op) |
C_028800_STENCIL_ENABLE & S_028800_DEPTH_BOUNDS_ENABLE(d->depth_bounds_test_enable ? 1 : 0) |
C_028800_BACKFACE_ENABLE & S_028800_STENCIL_ENABLE(d->stencil_test_enable ? 1 : 0) |
C_028800_STENCILFUNC & S_028800_BACKFACE_ENABLE(d->stencil_test_enable ? 1 : 0) |
C_028800_STENCILFUNC_BF; S_028800_STENCILFUNC(d->stencil_op.front.compare_op) |
S_028800_STENCILFUNC_BF(d->stencil_op.back.compare_op));
db_depth_control |= S_028800_Z_ENABLE(d->depth_test_enable ? 1 : 0) |
S_028800_Z_WRITE_ENABLE(d->depth_write_enable ? 1 : 0) |
S_028800_ZFUNC(d->depth_compare_op) |
S_028800_DEPTH_BOUNDS_ENABLE(d->depth_bounds_test_enable ? 1 : 0) |
S_028800_STENCIL_ENABLE(d->stencil_test_enable ? 1 : 0) |
S_028800_BACKFACE_ENABLE(d->stencil_test_enable ? 1 : 0) |
S_028800_STENCILFUNC(d->stencil_op.front.compare_op) |
S_028800_STENCILFUNC_BF(d->stencil_op.back.compare_op);
radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
} }
static void static void

22
src/amd/vulkan/radv_pipeline.c
View File

@@ -2200,15 +2200,9 @@ radv_pipeline_init_raster_state(struct radv_graphics_pipeline *pipeline,
const struct radv_device *device = pipeline->base.device; const struct radv_device *device = pipeline->base.device;
pipeline->pa_su_sc_mode_cntl = pipeline->pa_su_sc_mode_cntl =
S_028814_FACE(info->rs.front_face) |
S_028814_CULL_FRONT(!!(info->rs.cull_mode & VK_CULL_MODE_FRONT_BIT)) |
S_028814_CULL_BACK(!!(info->rs.cull_mode & VK_CULL_MODE_BACK_BIT)) |
S_028814_POLY_MODE(info->rs.polygon_mode != V_028814_X_DRAW_TRIANGLES) | S_028814_POLY_MODE(info->rs.polygon_mode != V_028814_X_DRAW_TRIANGLES) |
S_028814_POLYMODE_FRONT_PTYPE(info->rs.polygon_mode) | S_028814_POLYMODE_FRONT_PTYPE(info->rs.polygon_mode) |
S_028814_POLYMODE_BACK_PTYPE(info->rs.polygon_mode) | S_028814_POLYMODE_BACK_PTYPE(info->rs.polygon_mode) |
S_028814_POLY_OFFSET_FRONT_ENABLE(info->rs.depth_bias_enable) |
S_028814_POLY_OFFSET_BACK_ENABLE(info->rs.depth_bias_enable) |
S_028814_POLY_OFFSET_PARA_ENABLE(info->rs.depth_bias_enable) |
S_028814_PROVOKING_VTX_LAST(info->rs.provoking_vtx_last); S_028814_PROVOKING_VTX_LAST(info->rs.provoking_vtx_last);
if (device->physical_device->rad_info.gfx_level >= GFX10) { if (device->physical_device->rad_info.gfx_level >= GFX10) {
@@ -2221,7 +2215,6 @@ radv_pipeline_init_raster_state(struct radv_graphics_pipeline *pipeline,
S_028810_DX_CLIP_SPACE_DEF(!pipeline->negative_one_to_one) | S_028810_DX_CLIP_SPACE_DEF(!pipeline->negative_one_to_one) |
S_028810_ZCLIP_NEAR_DISABLE(info->rs.depth_clip_disable) | S_028810_ZCLIP_NEAR_DISABLE(info->rs.depth_clip_disable) |
S_028810_ZCLIP_FAR_DISABLE(info->rs.depth_clip_disable) | S_028810_ZCLIP_FAR_DISABLE(info->rs.depth_clip_disable) |
S_028810_DX_RASTERIZATION_KILL(info->rs.discard_enable) |
S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
pipeline->uses_conservative_overestimate = pipeline->uses_conservative_overestimate =
@@ -2248,10 +2241,8 @@ radv_pipeline_init_depth_stencil_state(struct radv_graphics_pipeline *pipeline,
{ {
const struct radv_physical_device *pdevice = pipeline->base.device->physical_device; const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
struct radv_depth_stencil_state ds_state = {0}; struct radv_depth_stencil_state ds_state = {0};
uint32_t db_depth_control = 0;
bool has_depth_attachment = info->ri.depth_att_format != VK_FORMAT_UNDEFINED; bool has_depth_attachment = info->ri.depth_att_format != VK_FORMAT_UNDEFINED;
bool has_stencil_attachment = info->ri.stencil_att_format != VK_FORMAT_UNDEFINED;
if (has_depth_attachment) { if (has_depth_attachment) {
/* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */ /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
@@ -2259,17 +2250,6 @@ radv_pipeline_init_depth_stencil_state(struct radv_graphics_pipeline *pipeline,
if (pdevice->rad_info.gfx_level >= GFX10_3) if (pdevice->rad_info.gfx_level >= GFX10_3)
ds_state.db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE(1); ds_state.db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE(1);
db_depth_control = S_028800_Z_ENABLE(info->ds.depth_test_enable) |
S_028800_Z_WRITE_ENABLE(info->ds.depth_write_enable) |
S_028800_ZFUNC(info->ds.depth_compare_op) |
S_028800_DEPTH_BOUNDS_ENABLE(info->ds.depth_bounds_test_enable);
}
if (has_stencil_attachment && info->ds.stencil_test_enable) {
db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
db_depth_control |= S_028800_STENCILFUNC(info->ds.front.compare_op);
db_depth_control |= S_028800_STENCILFUNC_BF(info->ds.back.compare_op);
} }
ds_state.db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | ds_state.db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
@@ -2305,8 +2285,6 @@ radv_pipeline_init_depth_stencil_state(struct radv_graphics_pipeline *pipeline,
S_028000_MAX_ALLOWED_TILES_IN_WAVE(max_allowed_tiles_in_wave); S_028000_MAX_ALLOWED_TILES_IN_WAVE(max_allowed_tiles_in_wave);
} }
pipeline->db_depth_control = db_depth_control;
return ds_state; return ds_state;
} }

1
src/amd/vulkan/radv_private.h
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@@ -2152,7 +2152,6 @@ struct radv_graphics_pipeline {
uint64_t needed_dynamic_state; uint64_t needed_dynamic_state;
unsigned tess_patch_control_points; unsigned tess_patch_control_points;
unsigned pa_su_sc_mode_cntl; unsigned pa_su_sc_mode_cntl;
unsigned db_depth_control;
unsigned pa_cl_clip_cntl; unsigned pa_cl_clip_cntl;
unsigned cb_color_control; unsigned cb_color_control;
uint32_t binding_stride[MAX_VBS]; uint32_t binding_stride[MAX_VBS];