diff --git a/src/amd/vulkan/nir/radv_nir_lower_io.c b/src/amd/vulkan/nir/radv_nir_lower_io.c
index d0e21786d6a..82d7e0a3da3 100644
--- a/src/amd/vulkan/nir/radv_nir_lower_io.c
+++ b/src/amd/vulkan/nir/radv_nir_lower_io.c
@@ -142,12 +142,12 @@ radv_nir_lower_io_to_mem(struct radv_device *device, struct radv_shader_stage *s
       }
    } else if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
       NIR_PASS_V(nir, ac_nir_lower_hs_inputs_to_mem, map_input, info->vs.tcs_in_out_eq);
-      NIR_PASS_V(nir, ac_nir_lower_hs_outputs_to_mem, radv_map_io_driver_location, pdev->info.gfx_level,
+      NIR_PASS_V(nir, ac_nir_lower_hs_outputs_to_mem, map_output, pdev->info.gfx_level,
                  info->tcs.tes_inputs_read, info->tcs.tes_patch_inputs_read, info->wave_size, false, false);
 
       return true;
    } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
-      NIR_PASS_V(nir, ac_nir_lower_tes_inputs_to_mem, radv_map_io_driver_location);
+      NIR_PASS_V(nir, ac_nir_lower_tes_inputs_to_mem, map_input);
 
       if (info->tes.as_es) {
          NIR_PASS_V(nir, ac_nir_lower_es_outputs_to_mem, map_output, pdev->info.gfx_level, info->esgs_itemsize);
diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c
index 86a59742210..c9eedf5a16b 100644
--- a/src/amd/vulkan/radv_pipeline_graphics.c
+++ b/src/amd/vulkan/radv_pipeline_graphics.c
@@ -1382,7 +1382,7 @@ radv_link_tcs(const struct radv_device *device, struct radv_shader_stage *tcs_st
    const uint64_t nir_mask = tcs_stage->nir->info.outputs_written & tes_stage->nir->info.inputs_read &
                              ~(VARYING_BIT_TESS_LEVEL_OUTER | VARYING_BIT_TESS_LEVEL_INNER);
    const uint64_t io_mask = radv_gather_unlinked_io_mask(nir_mask);
-   const unsigned num_reserved_outputs = util_last_bit64(io_mask);
+   const unsigned num_reserved_outputs = util_bitcount64(io_mask);
 
    /* Count the number of per-patch output slots we need to reserve for the TCS and TES.
     * This is necessary because we need it to determine the patch size in VRAM.
@@ -1390,7 +1390,7 @@ radv_link_tcs(const struct radv_device *device, struct radv_shader_stage *tcs_st
    const uint64_t patch_io_mask = radv_gather_unlinked_patch_io_mask(
       tcs_stage->nir->info.outputs_written & tes_stage->nir->info.inputs_read,
       tcs_stage->nir->info.patch_outputs_written & tes_stage->nir->info.patch_inputs_read);
-   const unsigned num_reserved_patch_outputs = util_last_bit64(patch_io_mask);
+   const unsigned num_reserved_patch_outputs = util_bitcount64(patch_io_mask);
 
    tcs_stage->info.tcs.num_linked_outputs = num_reserved_outputs;
    tcs_stage->info.tcs.num_linked_patch_outputs = num_reserved_patch_outputs;