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radv: update configuring COVERAGE_TO_SHADER_SELECT on GFX12

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This bit has been moved to SPI_PS_INPUT_ENA.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29566>
This commit is contained in:
Samuel Pitoiset
2024-06-05 12:30:37 +02:00
committed by Marge Bot
parent 27496928e4
commit be3c837c04
8 changed files with 24 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/amd/vulkan/radv_aco_shader_info.h
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@@ -39,8 +39,8 @@ radv_aco_convert_shader_info(struct aco_shader_info *aco_info, const struct radv
ASSIGN_FIELD(tcs.num_lds_blocks);
ASSIGN_FIELD(ps.num_interp);
ASSIGN_FIELD(cs.uses_full_subgroups);
aco_info->ps.spi_ps_input_ena = radv->ps.spi_ps_input;
aco_info->ps.spi_ps_input_addr = radv->ps.spi_ps_input;
aco_info->ps.spi_ps_input_ena = radv->ps.spi_ps_input_ena;
aco_info->ps.spi_ps_input_addr = radv->ps.spi_ps_input_addr;
aco_info->gfx9_gs_ring_lds_size = radv->gs_ring_info.lds_size;
aco_info->is_trap_handler_shader = radv->type == RADV_SHADER_TYPE_TRAP_HANDLER;
aco_info->image_2d_view_of_3d = radv_key->image_2d_view_of_3d;

4
src/amd/vulkan/radv_cmd_buffer.c
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@@ -5699,7 +5699,9 @@ radv_emit_msaa_state(struct radv_cmd_buffer *cmd_buffer)
db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
}
pa_sc_aa_config |= S_028BE0_COVERAGE_TO_SHADER_SELECT(ps && ps->info.ps.reads_fully_covered);
/* GFX12 programs it in SPI_PS_INPUT_ENA.COVERAGE_TO_SHADER_SELECT */
pa_sc_aa_config |=
S_028BE0_COVERAGE_TO_SHADER_SELECT(pdev->info.gfx_level < GFX12 && ps && ps->info.ps.reads_fully_covered);
if (pdev->info.gfx_level >= GFX12) {
radeon_set_context_reg(cmd_buffer->cs, R_028C5C_PA_SC_SAMPLE_PROPERTIES,

8
src/amd/vulkan/radv_pipeline.c
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@@ -525,10 +525,10 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
.no_color_export = stage->info.has_epilog,
.no_depth_export = stage->info.ps.exports_mrtz_via_epilog,
.bc_optimize_for_persp = G_0286CC_PERSP_CENTER_ENA(stage->info.ps.spi_ps_input) &&
G_0286CC_PERSP_CENTROID_ENA(stage->info.ps.spi_ps_input),
.bc_optimize_for_linear = G_0286CC_LINEAR_CENTER_ENA(stage->info.ps.spi_ps_input) &&
G_0286CC_LINEAR_CENTROID_ENA(stage->info.ps.spi_ps_input),
.bc_optimize_for_persp = G_0286CC_PERSP_CENTER_ENA(stage->info.ps.spi_ps_input_ena) &&
G_0286CC_PERSP_CENTROID_ENA(stage->info.ps.spi_ps_input_ena),
.bc_optimize_for_linear = G_0286CC_LINEAR_CENTER_ENA(stage->info.ps.spi_ps_input_ena) &&
G_0286CC_LINEAR_CENTROID_ENA(stage->info.ps.spi_ps_input_ena),
};
if (!options.no_color_export) {

6
src/amd/vulkan/radv_shader.c
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@@ -3256,7 +3256,8 @@ radv_get_shader_name(const struct radv_shader_info *info, gl_shader_stage stage)
}
unsigned
radv_compute_spi_ps_input(const struct radv_graphics_state_key *gfx_state, const struct radv_shader_info *info)
radv_compute_spi_ps_input(const struct radv_physical_device *pdev, const struct radv_graphics_state_key *gfx_state,
const struct radv_shader_info *info)
{
unsigned spi_ps_input;
@@ -3287,7 +3288,8 @@ radv_compute_spi_ps_input(const struct radv_graphics_state_key *gfx_state, const
}
if (info->ps.reads_sample_mask_in || info->ps.reads_fully_covered) {
spi_ps_input |= S_0286CC_SAMPLE_COVERAGE_ENA(1);
spi_ps_input |= S_0286CC_SAMPLE_COVERAGE_ENA(1) |
S_02865C_COVERAGE_TO_SHADER_SELECT(pdev->info.gfx_level >= GFX12 && info->ps.reads_fully_covered);
}
if (G_0286CC_POS_W_FLOAT_ENA(spi_ps_input)) {

3
src/amd/vulkan/radv_shader.h
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@@ -583,7 +583,8 @@ unsigned radv_get_max_scratch_waves(const struct radv_device *device, struct rad
const char *radv_get_shader_name(const struct radv_shader_info *info, gl_shader_stage stage);
unsigned radv_compute_spi_ps_input(const struct radv_graphics_state_key *gfx_state,
unsigned radv_compute_spi_ps_input(const struct radv_physical_device *pdev,
const struct radv_graphics_state_key *gfx_state,
const struct radv_shader_info *info);
bool radv_can_dump_shader(struct radv_device *device, nir_shader *nir, bool meta_shader);

2
src/amd/vulkan/radv_shader_args.c
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@@ -276,7 +276,7 @@ declare_ps_input_vgprs(const struct radv_shader_info *info, struct radv_shader_a
ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* fixed pt */
if (args->remap_spi_ps_input)
ac_compact_ps_vgpr_args(&args->ac, info->ps.spi_ps_input);
ac_compact_ps_vgpr_args(&args->ac, info->ps.spi_ps_input_ena);
}
static void

7
src/amd/vulkan/radv_shader_info.c
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@@ -902,7 +902,12 @@ gather_shader_info_fs(const struct radv_device *device, const nir_shader *nir,
info->ps.pops_is_per_sample =
info->ps.pops && (nir->info.fs.sample_interlock_ordered || nir->info.fs.sample_interlock_unordered);
info->ps.spi_ps_input = radv_compute_spi_ps_input(gfx_state, info);
info->ps.spi_ps_input_ena = radv_compute_spi_ps_input(pdev, gfx_state, info);
info->ps.spi_ps_input_addr = info->ps.spi_ps_input_ena;
if (pdev->info.gfx_level >= GFX12) {
/* Only SPI_PS_INPUT_ENA has this bit on GFX12. */
info->ps.spi_ps_input_addr &= C_02865C_COVERAGE_TO_SHADER_SELECT;
}
info->has_epilog = gfx_state->ps.has_epilog && info->ps.colors_written;

3
src/amd/vulkan/radv_shader_info.h
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@@ -203,7 +203,8 @@ struct radv_shader_info {
bool pops; /* Uses Primitive Ordered Pixel Shading (fragment shader interlock) */
bool pops_is_per_sample;
bool mrt0_is_dual_src;
unsigned spi_ps_input;
unsigned spi_ps_input_ena;
unsigned spi_ps_input_addr;
unsigned colors_written;
unsigned spi_shader_col_format;
unsigned cb_shader_mask;