OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

nvc0: update tic in-place when buffer address changes

Browse Source 
This is helpful for bindless, where changing TIC id's is undesirable.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
Ilia Mirkin
2017-12-30 01:07:30 -05:00
parent adcd241b56
commit bdf300e09d
2 changed files with 21 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/gallium/drivers/nouveau/nvc0/nvc0_context.h
View File

@@ -345,7 +345,7 @@ void nvc0_validate_surfaces(struct nvc0_context *);
void nve4_set_surface_info(struct nouveau_pushbuf *, struct pipe_image_view *,
struct nvc0_context *);
void nvc0_mark_image_range_valid(const struct pipe_image_view *);
void nvc0_update_tic(struct nvc0_context *, struct nv50_tic_entry *,
bool nvc0_update_tic(struct nvc0_context *, struct nv50_tic_entry *,
struct nv04_resource *);
struct pipe_sampler_view *

33
src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
View File

@@ -449,23 +449,30 @@ nvc0_create_texture_view(struct pipe_context *pipe,
return gf100_create_texture_view(pipe, texture, templ, flags, target);
}
void
bool
nvc0_update_tic(struct nvc0_context *nvc0, struct nv50_tic_entry *tic,
struct nv04_resource *res)
{
uint64_t address = res->address;
if (res->base.target != PIPE_BUFFER)
return;
return false;
address += tic->pipe.u.buf.offset;
if (tic->tic[1] == (uint32_t)address &&
(tic->tic[2] & 0xff) == address >> 32)
return;
return false;
nvc0_screen_tic_unlock(nvc0->screen, tic);
tic->id = -1;
tic->tic[1] = address;
tic->tic[2] &= 0xffffff00;
tic->tic[2] |= address >> 32;
if (tic->id >= 0) {
nvc0->base.push_data(&nvc0->base, nvc0->screen->txc, tic->id * 32,
NV_VRAM_DOMAIN(&nvc0->screen->base), 32,
tic->tic);
return true;
}
return false;
}
bool
@@ -488,14 +495,14 @@ nvc0_validate_tic(struct nvc0_context *nvc0, int s)
continue;
}
res = nv04_resource(tic->pipe.texture);
nvc0_update_tic(nvc0, tic, res);
need_flush |= nvc0_update_tic(nvc0, tic, res);
if (tic->id < 0) {
tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
nvc0_m2mf_push_linear(&nvc0->base, nvc0->screen->txc, tic->id * 32,
NV_VRAM_DOMAIN(&nvc0->screen->base), 32,
tic->tic);
nvc0->base.push_data(&nvc0->base, nvc0->screen->txc, tic->id * 32,
NV_VRAM_DOMAIN(&nvc0->screen->base), 32,
tic->tic);
need_flush = true;
} else
if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
@@ -554,14 +561,14 @@ nve4_validate_tic(struct nvc0_context *nvc0, unsigned s)
continue;
}
res = nv04_resource(tic->pipe.texture);
nvc0_update_tic(nvc0, tic, res);
need_flush |= nvc0_update_tic(nvc0, tic, res);
if (tic->id < 0) {
tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
nve4_p2mf_push_linear(&nvc0->base, nvc0->screen->txc, tic->id * 32,
NV_VRAM_DOMAIN(&nvc0->screen->base), 32,
tic->tic);
nvc0->base.push_data(&nvc0->base, nvc0->screen->txc, tic->id * 32,
NV_VRAM_DOMAIN(&nvc0->screen->base), 32,
tic->tic);
need_flush = true;
} else
if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {