i965: Don't set up VUE space for the disabled user clip distances on gen6.
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@@ -218,7 +218,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
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c->first_overflow_output = 0;
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c->first_overflow_output = 0;
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if (intel->gen >= 6)
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if (intel->gen >= 6)
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mrf = 6;
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mrf = 4;
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else if (intel->gen == 5)
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else if (intel->gen == 5)
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mrf = 8;
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mrf = 8;
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else
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else
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@@ -318,8 +318,11 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
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*/
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*/
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attributes_in_vue = MAX2(c->nr_outputs, c->nr_inputs);
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attributes_in_vue = MAX2(c->nr_outputs, c->nr_inputs);
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/* See emit_vertex_write() for where the VUE's overhead on top of the
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* attributes comes from.
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*/
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if (intel->gen >= 6)
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if (intel->gen >= 6)
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c->prog_data.urb_entry_size = (attributes_in_vue + 4 + 7) / 8;
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c->prog_data.urb_entry_size = (attributes_in_vue + 2 + 7) / 8;
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else if (intel->gen == 5)
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else if (intel->gen == 5)
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c->prog_data.urb_entry_size = (attributes_in_vue + 6 + 3) / 4;
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c->prog_data.urb_entry_size = (attributes_in_vue + 6 + 3) / 4;
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else
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else
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@@ -1364,16 +1367,19 @@ static void emit_vertex_write( struct brw_vs_compile *c)
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*/
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*/
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brw_set_access_mode(p, BRW_ALIGN_1);
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brw_set_access_mode(p, BRW_ALIGN_1);
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/* The VUE layout is documented in Volume 2a. */
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if (intel->gen >= 6) {
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if (intel->gen >= 6) {
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/* There are 16 DWs (D0-D15) in VUE header on Sandybridge:
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/* There are 8 or 16 DWs (D0-D15) in VUE header on Sandybridge:
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* dword 0-3 (m1) of the header is indices, point width, clip flags.
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* dword 0-3 (m1) of the header is indices, point width, clip flags.
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* dword 4-7 (m2) is the 4D space position
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* dword 4-7 (m2) is the 4D space position
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* dword 8-15 (m3,m4) of the vertex header is the user clip distance.
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* dword 8-15 (m3,m4) of the vertex header is the user clip distance if
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* m5 is the first vertex data we fill, which is the vertex position.
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* enabled. We don't use it, so skip it.
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* m3 is the first vertex element data we fill, which is the vertex
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* position.
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*/
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*/
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brw_MOV(p, offset(m0, 2), pos);
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brw_MOV(p, offset(m0, 2), pos);
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brw_MOV(p, offset(m0, 5), pos);
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brw_MOV(p, offset(m0, 3), pos);
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len_vertex_header = 4;
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len_vertex_header = 2;
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} else if (intel->gen == 5) {
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} else if (intel->gen == 5) {
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/* There are 20 DWs (D0-D19) in VUE header on Ironlake:
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/* There are 20 DWs (D0-D19) in VUE header on Ironlake:
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* dword 0-3 (m1) of the header is indices, point width, clip flags.
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* dword 0-3 (m1) of the header is indices, point width, clip flags.
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@@ -69,7 +69,7 @@ upload_sf_state(struct brw_context *brw)
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dw1 =
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dw1 =
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num_outputs << GEN6_SF_NUM_OUTPUTS_SHIFT |
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num_outputs << GEN6_SF_NUM_OUTPUTS_SHIFT |
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(num_inputs + 1) / 2 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
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(num_inputs + 1) / 2 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
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3 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT;
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1 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT;
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dw2 = GEN6_SF_VIEWPORT_TRANSFORM_ENABLE |
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dw2 = GEN6_SF_VIEWPORT_TRANSFORM_ENABLE |
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GEN6_SF_STATISTICS_ENABLE;
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GEN6_SF_STATISTICS_ENABLE;
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dw3 = 0;
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dw3 = 0;
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