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ir3_nir_opt_preamble: handle 8-bit preamble loads and stores

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Support 8-bit loads and stores in the preamble alongside 16-bit ones by
employing the correct conversion variants. Promotions to float remain
specific to 16-bit loads and stores.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28254>
This commit is contained in:
Zan Dobersek
2024-03-18 20:47:38 +01:00
committed by Marge Bot
parent a9b781fa54
commit bc542b5827
1 changed files with 4 additions and 4 deletions
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8
src/freedreno/ir3/ir3_nir_opt_preamble.c
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@@ -378,12 +378,12 @@ ir3_nir_lower_preamble(nir_shader *nir, struct ir3_shader_variant *v)
if (dest->bit_size == 1) { if (dest->bit_size == 1) {
new_dest = nir_i2b(b, new_dest); new_dest = nir_i2b(b, new_dest);
} else if (dest->bit_size != 32) { } else if (dest->bit_size != 32) {
assert(dest->bit_size == 16);
if (all_uses_float(dest, true)) { if (all_uses_float(dest, true)) {
assert(dest->bit_size == 16);
new_dest = nir_f2f16(b, new_dest); new_dest = nir_f2f16(b, new_dest);
BITSET_SET(promoted_to_float, nir_intrinsic_base(intrin)); BITSET_SET(promoted_to_float, nir_intrinsic_base(intrin));
} else { } else {
new_dest = nir_u2u16(b, new_dest); new_dest = nir_u2uN(b, new_dest, dest->bit_size);
} }
} }
@@ -413,8 +413,8 @@ ir3_nir_lower_preamble(nir_shader *nir, struct ir3_shader_variant *v)
if (src->bit_size == 1) if (src->bit_size == 1)
src = nir_b2i32(b, src); src = nir_b2i32(b, src);
if (src->bit_size != 32) { if (src->bit_size != 32) {
assert(src->bit_size == 16); if (BITSET_TEST(promoted_to_float, nir_intrinsic_base(intrin))){
if (BITSET_TEST(promoted_to_float, nir_intrinsic_base(intrin))) { assert(src->bit_size == 16);
src = nir_f2f32(b, src); src = nir_f2f32(b, src);
} else { } else {
src = nir_u2u32(b, src); src = nir_u2u32(b, src);